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TWL1200
SCES786A JUNE 2009REVISED NOVEMBER 2009
www.ti.com
Typical Application Wiring for TWL1200 When Connecting to the WL1271
Table 2. WL1271+TWL1200 Interface
HOST BALL BALL WL1271
PIN NAME TYPE TYPE PIN NAME
(MSM) NO. NO. COB
VCCA C4 Power (3.0 V) Power (1.8 V) C5 VCCB
VCCA D4 Power (3.0 V) Power (1.8 V) D5 VCCB
SDIO_DATA0(A) B2 I/O I/O B6 SDIO_DATA0(B) K4
SDIO_DATA1(A) C2 I/O I/O C6 SDIO_DATA1(B) J4
SDIO_DATA2(A) C1 I/O I/O C7 SDIO_DATA2(B) J3
SDIO_DATA3(A) B1 I/O I/O B7 SDIO_DATA3(B) J5
SDIO_CMD(A) A2 I/O I/O A6 SDIO_CMD(B) L3
SDIO_CLK(A) A1 I O A7 SDIO_CLK(B) M3
WLAN_EN(A) D1 I O D6 WLAN_EN(B) J2
WLAN_IRQ(A) D2 O I D7 WLAN_IRQ(B) G4
CLK_REQ(A) E1 O I E7 CLK_REQ(B) F5
BT_EN(A) E2 I O E6 BT_EN(B) G5
BT_UART_RX(A) G1 I TWL1200 O G7 BT_UART_RX(B) G7
BT_UART_CTS(A) F1 I O F7 BT_UART_CTS(B) E11
BT_UART_TX(A) G2 O I G6 BT_UART_TX(B) G8
BT_UART_RTS(A) F2 O I F6 BT_UART_RTS(B) G11
AUDIO_IN(A) F3 I I/O F5 AUDIO_IN(B) F6
AUDIO_CLK(A) A3 I/O I/O A5 AUDIO_CLK(B) F8
AUDIO_F-SYN(A) B3 I/O I/O B5 AUDIO_F-SYN(B) H11
AUDIO_OUT(A) G3 O I G5 AUDIO_OUT(B) F7
SLOW_CLK(A) G4 I O F4 SLOW_CLK(B) K9
AUD_DIR A4 I GND D3 GND
OE B4 active low E3 GND
E4 GND
E5 GND
20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
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TWL1200ZQCR 数据手册

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