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UC3525BDW 数据手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
稳压芯片
封装:
SOIC-16
描述:
TEXAS INSTRUMENTS UC3525BDW 调整脉冲宽度调制器, 35V-8V电源, 500 kHz, 18V/100mA输出, SOIC-16
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UC3525BDW数据手册
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UC1525B UC1527B
UC2525B UC2527B
UC3525B UC3527B
DESCRIPTION
The UC1525B/1527B series of pulse width modulator integrated circuits
are designed to offer improved performance and lowered external parts
count when used in designing all types of switching power supplies. The
on-chip +5.1V buried zener reference is trimmed to ±0.75% and the input
common-mode range of the error amplifier includes the reference voltage,
eliminating external resistors. A sync input to the oscillator allows multiple
units to be slaved or a single unit to be synchronized to an external system
clock. A single resistor between the CT and the discharge terminals provide
a wide range of dead time adjustment. These devices also feature built-in
soft-start circuitry with only an external timing capacitor required. A shut-
down terminal controls both the soft-start circuitry and the output stages,
providing instantaneous turn off through the PWM latch with pulsed shut-
down, as well as soft-start recycle with longer shutdown commands. These
functions are also controlled by an undervoltage lockout which keeps the
outputs off and the soft-start capacitor discharged for sub-normal input volt-
ages. This lockout circuitry includes approximately 500mV of hysteresis for
jitter-free operation. Another feature of these PWM circuits is a latch follow-
ing the comparator. Once a PWM pulse has been terminated for any rea-
son, the outputs will remain off for the duration of the period. The latch is
reset with each clock pulse. The output stages are totem-pole designs ca-
pable of sourcing or sinking in excess of 200mA. The UC1525B output
stage features NOR logic, giving a LOW output for an OFF state. The
UC1527B utilizes OR logic which results in a HIGH output level when OFF.
Regulating Pulse Width Modulators
FEATURES
• 8 to 35V Operation
• 5.1V Buried Zener Reference
Trimmed to ±0.75%
• 100Hz to 500kHz Oscillator Range
• Separate Oscillator Sync Terminal
• Adjustable Deadtime Control
• Internal Soft-Start
• Pulse-by-Pulse Shutdown
• Input Undervoltage Lockout with
Hysteresis
• Latching PWM to Prevent Multiple
Pulses
• Dual Source/Sink Output Drivers
• Low Cross Conduction Output Stage
• Tighter Reference Specifications
SLUS376 JULY 1995
BLOCK DIAGRAM
UDG-95055
application
INFO
available
UC3527B
Not Recommended For New Designs
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