Datasheet 搜索 > 存储芯片 > Winbond Electronics（华邦电子股份） > W29N01GVSIAA 数据手册 > W29N01GVSIAA 数据手册 2/70 页
器件3D模型￥ 5.724
W29N01GVSIAA 数据手册 - Winbond Electronics（华邦电子股份）
制造商:
Winbond Electronics（华邦电子股份）
分类:
存储芯片
封装:
TFSOP-48
描述:
1-Gbit(128M x 8bit)，并行接口，工作电压：2.7V to 3.6V
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P8P9P10P11P12Hot
原理图在P13
封装尺寸在P8P65
型号编码规则在P68
标记信息在P69
封装信息在P7
功能描述在P7
技术参数、封装参数在P48
电气规格在P48P50
型号编号列表在P68P69
导航目录
W29N01GVSIAA数据手册
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of 70 Go
若手册格式错乱，请下载阅览PDF原文件
W29N01GV
Release Date: January 11
th
, 2018
2 Revision H
Table of Contents
1. GENERAL DESCRIPTION ............................................................................................................... 7
2. FEATURES ....................................................................................................................................... 7
3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 8
3.1 Pin assignment 48-pin TSOP1 ............................................................................................. 8
3.2 Pin assignment 48 ball VFBGA ............................................................................................ 9
3.3 Pin assignment 63 ball VFBGA .......................................................................................... 10
3.4 Pin Descriptions .................................................................................................................. 11
4. PIN DESCRIPTIONS ...................................................................................................................... 12
4.1 Chip Enable (#CE) .............................................................................................................. 12
4.2 Write Enable (#WE) ............................................................................................................ 12
4.3 Read Enable (#RE) ............................................................................................................ 12
4.4 Address Latch Enable (ALE) .............................................................................................. 12
4.5 Command Latch Enable (CLE) .......................................................................................... 12
4.6 Write Protect (#WP) ............................................................................................................ 12
4.7 Ready/Busy (RY/#BY) ........................................................................................................ 12
4.8 Input and Output (I/Ox) ....................................................................................................... 12
5. BLOCK DIAGRAM .......................................................................................................................... 13
6. MEMORY ARRAY ORGANIZATION .............................................................................................. 14
6.1 Array Organization .............................................................................................................. 14
7. MODE SELECTION TABLE ........................................................................................................... 15
8. COMMAND TABLE......................................................................................................................... 16
9. DEVICE OPERATIONS .................................................................................................................. 17
9.1 READ operation .................................................................................................................. 17
9.1.1 PAGE READ (00h-30h)......................................................................................................... 17
9.1.2 CACHE READ OPERATIONS .............................................................................................. 18
9.1.3 RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 22
9.1.4 READ ID (90h) ...................................................................................................................... 23
9.1.5 READ PARAMETER PAGE (ECh) ....................................................................................... 24
9.1.6 READ STATUS (70h)............................................................................................................ 26
9.1.7 READ UNIQUE ID (EDh) ...................................................................................................... 28
9.2 PROGRAM operation ......................................................................................................... 29
9.2.1 PAGE PROGRAM (80h-10h) ................................................................................................ 29
9.2.2 SERIAL DATA INPUT (80h) .................................................................................................. 29
9.2.3 RANDOM DATA INPUT (85h) .............................................................................................. 30
9.2.4 CACHE PROGRAM (80h-15h) ............................................................................................. 30
9.3 COPY BACK operation....................................................................................................... 32
9.3.1 READ for COPY BACK (00h-35h) ........................................................................................ 32
9.3.2 PROGRAM for COPY BACK (85h-10h) ................................................................................ 32
9.4 BLOCK ERASE operation .................................................................................................. 34
9.4.1 BLOCK ERASE (60h-D0h) .................................................................................................... 34
9.5 RESET operation ................................................................................................................ 35
9.5.1 RESET (FFh) ........................................................................................................................ 35
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