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器件3D模型￥ 651.815
AD5791BRUZ 其他数据使用手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
分类:
DA转换器
封装:
TSSOP-20
描述:
ANALOG DEVICES AD5791BRUZ 数模转换器, 20 bit, 1 MSPS, 串行, 2.7V 至 5.5V, TSSOP, 20 引脚
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AD5791BRUZ数据手册
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Data Sheet AD5791
Rev. D | Page 5 of 28
TIMING CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter
Limit
1
Unit Test Conditions/Comments
IOV
CC
= 1.71 V to 3.3 V IOV
CC
= 3.3 V to 5.5 V
t
1
2
40 28 ns min SCLK cycle time
92 60 ns min SCLK cycle time (readback mode)
t
2
15 10 ns min SCLK high time
t
3
9 5 ns min SCLK low time
t
4
5 5 ns min
SYNC
to SCLK falling edge setup time
t
5
2 2 ns min SCLK falling edge to
SYNC
rising edge hold time
t
6
48 40 ns min Minimum
SYNC
high time
t
7
8 6 ns min
SYNC
rising edge to next SCLK falling edge ignore
t
8
9 7 ns min Data setup time
t
9
12 7 ns min Data hold time
t
10
13 10 ns min
LDAC
falling edge to
SYNC
falling edge
t
11
20 16 ns min
SYNC
rising edge to
LDAC
falling edge
t
12
14 11 ns min
LDAC
pulse width low
t
13
130 130 ns typ
LDAC
falling edge to output response time
t
14
130 130 ns typ
SYNC
rising edge to output response time (
LDAC
tied low)
t
15
50 50 ns min
CLR
pulse width low
t
16
140 140 ns typ
CLR
pulse activation time
t
17
0 0 ns min
SYNC
falling edge to first SCLK rising edge
t
18
65 60 ns max
SYNC
rising edge to SDO tristate (C
L
= 50 pF)
t
19
62 45 ns max SCLK rising edge to SDO valid (C
L
= 50 pF)
t
20
0
0
ns min
SYNC
rising edge to SCLK rising edge ignore
t
21
35 35 ns typ
RESET
pulse width low
t
22
150 150 ns typ
RESET
pulse activation time
1
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of IOV
CC
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes.
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