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AD8153ACPZ
器件3D模型
4.544
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AD8153ACPZ数据手册
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3.2 Gbps
Sin
g
le Buffered Mux/Demux Switch
Data Sheet
AD8153
Rev. A Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Single lane 2:1 mux/1:2 demux
3.2 Gbps to dc data rates
Compensates over 40 inches of FR4 at 3.2 Gbps through
Two levels of input equalization, or
Four levels of output pre-emphasis
Operates with ac- or dc-coupled differential I/O
Low deterministic jitter, typically 16 ps p-p
Low random jitter, typically 500 fs rms
On-chip terminations
Unicast or bicast on 1:2 demux function
Loopback capability on all ports
3.3 V core supply
Flexible I/O supply
Low power, typically 200 mW in basic configuration
1
32-lead LFCSP package
−40°C to +85°C operating temperature range
APPLICATIONS
Low cost redundancy switch
SONET OC48/SDH16 and lower data rates
Gigabit Ethernet over backplane
Fibre Channel 1.06 Gbps and 2.12 Gbps over backplane
Serial RapidIO
PCI Express Gen 1
Infiniband over backplane
FUNCTIONAL BLOCK DIAGRAM
RECEIVE
EQUALIZATION
TRANSMIT
PRE-EMPHASIS
2:1 MULTIPLEXER/
1:2 DEMULTIPLEXER
TRANSMIT
PRE-EMPHASIS
RECEIVE
EQUALIZATION
CONTROL
LOGIC
SEL
BICAST
LB_A
LB_B
LB_C
MODE
RESETB
EQ_A/(SCL)
EQ_B/(SDA)
EQ_C
PE_A/(I2C_A[0])
PE_B/(I2C_A[1])
PE_C/(I2C_A[2])
INPUT A
INPUT B
OUTPUT A
OUTPUT B
OUTPUT C
INPUT C
AD8153
06393-001
EQ
EQ
EQ
Figure 1.
GENERAL DESCRIPTION
The AD8153 is an asynchronous, protocol agnostic, single-lane
2:1 switch with three differential CML inputs and three differential
CML outputs. The AD8159, another member of the Xstream
line of products, is suitable for similar applications that require
more than one lane.
The AD8153 is optimized for NRZ signaling with data rates of
up to 3.2 Gbps per port. Each port offers two levels of input
equalization and four levels of output pre-emphasis.
The device consists of a 2:1 multiplexer and a 1:2 demultiplexer.
There are three operating modes: pin mode, serial mode, and
mixed mode. In pin mode, lane switching, equalization, and
pre-emphasis are controlled exclusively using external pins. In
serial mode, an I
2
C interface is used to control the device and to
provide access to advanced features, such as additional pre-
emphasis settings and output disable. In mixed mode, the user
accesses the advanced features using I
2
C, but controls lane
switching using the external pins.
The main application of the AD8153 is to support redundancy
on both the backplane side and the line interface side of a serial
link. The device has unicast and bicast capability, so it is capable
of supporting either 1 + 1 or 1:1 redundancy.
Using a mixture of bicast and loopback modes, the AD8153 can
also be used to test high speed serial links by duplicating the
incoming data and transmitting it to the destination port and
test equipment simultaneously.
1
Two ports active with no pre-emphasis.

AD8153ACPZ 数据手册

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AD8153 数据手册

ADI(亚德诺)
3.2 Gbps的一个缓冲器,复用器/解复用器开关 3.2 Gbps Single Buffered Mux/Demux Switch
ADI(亚德诺)
ANALOG DEVICES  AD8153ACPZ  芯片, 模拟多路复用器/信号分离器, 2:1, LFCSP-32
ADI(亚德诺)
3.2 Gbps的一个缓冲器,复用器/解复用器开关 3.2 Gbps Single Buffered Mux/Demux Switch
ADI(亚德诺)
3.2 Gbps的一个缓冲器,复用器/解复用器开关 3.2 Gbps Single Buffered Mux/Demux Switch
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