Datasheet 搜索 > 接口隔离器 > ADI（亚德诺） > ADUM1400BRW-RL 数据手册 > ADUM1400BRW-RL 其他数据使用手册 5/31 页
器件3D模型￥ 5.16
ADUM1400BRW-RL 其他数据使用手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
分类:
接口隔离器
封装:
SOIC-16
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P22P23P24Hot
原理图在P1
封装尺寸在P30
型号编码规则在P1P30
封装信息在P19P30
功能描述在P1P22P23P24
技术参数、封装参数在P1P4P6P8P9P11P13P15P17P19P21P27
应用领域在P1P27P30
电气规格在P4P6P8P11P13P15P17P25
导航目录
ADUM1400BRW-RL数据手册
Page:
of 31 Go
若手册格式错乱，请下载阅览PDF原文件
Data Sheet ADuM1400/ADuM1401/ADuM1402
Parameter Symbol Min Typ Max Unit Test Conditions
Pulse Width Distortion, |t
PLH
− t
PHL
|
5
PWD 40 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 11 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
6
t
PSK
50 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching
7
t
PSKCD
/t
PSKOD
50 ns C
L
= 15 pF, CMOS signal levels
ADuM1400/ADuM1401/ADuM1402BRW
Minimum Pulse Width
3
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
4
10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
5
t
PHL
, t
PLH
20
32
50
ns
C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
5
PWD 3 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
6
t
PSK
15 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels
7
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels
7
t
PSKOD
6 ns C
L
= 15 pF, CMOS signal levels
ADuM1400/ADuM1401/ADuM1402CRW
Minimum Pulse Width
3
PW 8.3 11.1 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
4
90 120 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
5
t
PHL
, t
PLH
18 27 32 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
5
PWD 0.5 2 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
6
t
PSK
10 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels
7
t
PSKCD
2 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels
7
t
PSKOD
5 ns C
L
= 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
t
PHZ
, t
PLH
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
t
PZH
, t
PZL
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
2.5 ns C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic
High Output
8
|CM
H
| 25 35 kV/µs V
Ix
= V
DD1
or V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at Logic
Low Output
8
|CM
L
| 25 35 kV/µs V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
1.2 Mbps
Input Dynamic Supply Current per Channel
9
I
DDI (D)
0.19 mA/Mbps
Output Dynamic Supply Current per Channel
9
I
DDO (D)
0.05 mA/Mbps
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
DD1
and V
DD2
supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
6
t
PSK
is the magnitude of the worst-case difference in t
PHL
or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. J | Page 5 of 31
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
