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ISPGAL22V10C-15LK 产品设计图 - Lattice Semiconductor（莱迪思）
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Lattice Semiconductor（莱迪思）
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CPLD芯片
封装:
SSOP-28
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封装尺寸在P3P4P5P6P9P12P13P14P15P23P24P31
标记信息在P25P26P27P28P39P54P55P61P68P70P122
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ISPGAL22V10C-15LK数据手册
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www.latticesemi.com 1 pkg_5.2
Package Diagrams
June 2016 Data Sheet
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16-Ball WLCS Package Option 1: iCE40 LP
Dimensions in Millimeters
C
ccc
C
1
A
A
aaa
(4X)
.015
.05
B
M
M
C
C A
PIN #1 ID FIDUCIAL
LOCATED IN THIS AREA
REF.
Min. Nom. Max.
A
A1
b
D
E
D1
E1
e
aaa
ccc
r
s
0.413
0.122
0.188
0.452
0.152
0.218
0.491
0.182
0.248
1.40 BSC
1.48 BSC
1.05 BSC
1.05 BSC
0.35 BSC
0.03
0.03
0.175
0.215
4
E1
e
s
D1
e
r
A
B
C
D
3
.16 X b
Ø
Ø
Ø
5
E
B
A
D
ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M - 1994.
ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSION “b” IS MEASURES AT THE MAXIMUM BUMP DIAMETER
PARALLEL TO PRIMARY DATUM C.
PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BUMPS.
BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE
PACKAGE BODY.
NOTES:
3
4
5
1.
2.
4
3
2
1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
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