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KC80526LY400128SL544 其他数据使用手册 - Intel（英特尔）
制造商:
Intel（英特尔）
分类:
微处理器
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BGA-495
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KC80526LY400128SL544数据手册
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Datasheet 3
Intel
®
Celeron
®
Processor – LP/ULP
Contents
1.0 Introduction....................................................................................................................................9
1.1 Overview.............................................................................................................................10
1.2 Terminology........................................................................................................................10
1.3 References .........................................................................................................................11
2.0 Intel
®
Celeron
®
Processor – LP/ULP Features .........................................................................11
2.1 Features in the Intel
®
Celeron
®
Processor – LP/ULP.........................................................11
2.1.1 On-die GTL+ Termination......................................................................................11
2.1.2 Streaming SIMD Extensions..................................................................................11
2.2 Power Management............................................................................................................12
2.2.1 Clock Control Architecture.....................................................................................12
2.2.2 Normal State..........................................................................................................12
2.2.3 Auto Halt State.......................................................................................................12
2.2.4 Stop Grant State....................................................................................................13
2.2.5 Quick Start State....................................................................................................14
2.2.6 HALT/Grant Snoop State.......................................................................................14
2.2.7 Sleep State ............................................................................................................14
2.2.8 Deep Sleep State...................................................................................................15
2.2.9 Operating System Implications of Low-power States ............................................15
2.2.10 GTL+ Signals.........................................................................................................15
2.2.11 Intel
®
Celeron
®
Processor – LP/ULP CPUID.........................................................16
3.0 Electrical Specifications.............................................................................................................17
3.1 Processor System Signals..................................................................................................17
3.1.1 Power Sequencing Requirements .........................................................................18
3.1.2 Test Access Port (TAP) Connection......................................................................18
3.1.3 Catastrophic Thermal Protection ...........................................................................19
3.1.4 Unused Signals......................................................................................................19
3.1.5 Signal State in Low-power States..........................................................................19
3.1.5.1 System Bus Signals...............................................................................19
3.1.5.2 CMOS and Open-drain Signals .............................................................19
3.1.5.3 Other Signals .........................................................................................20
3.2 Power Supply Requirements ..............................................................................................20
3.2.1 Decoupling Recommendations..............................................................................20
3.2.2 Voltage Planes.......................................................................................................20
3.3 System Bus Clock and Processor Clocking........................................................................21
3.4 Maximum Ratings...............................................................................................................21
3.5 DC Specifications ...............................................................................................................23
3.6 AC Specifications................................................................................................................26
3.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC Specifications ........26
4.0 System Signal Simulations.........................................................................................................35
4.1 System Bus Clock (BCLK) and PICCLK AC Signal Quality Specifications ........................35
4.2 GTL+ AC Signal Quality Specifications ..............................................................................36
4.3 Non-GTL+ Signal Quality Specifications.............................................................................40
4.3.1 PWRGOOD Signal Quality Specifications.............................................................40
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