Datasheet 搜索 > NXP（恩智浦） > LPC2101FBD48 数据手册 > LPC2101FBD48 其他数据使用手册 1/78 页
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LPC2101FBD48 其他数据使用手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
封装:
LQFP
描述:
单芯片16位/ 32位微控制器; 8 KB / 16 KB / 32 KB闪存， ISP / IAP ，快速端口和10位ADC Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC
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封装尺寸在P62P63P64P65P66
型号编码规则在P3P4
焊接温度在P67P68P69P70P71
功能描述在P1P17
技术参数、封装参数在P74
应用领域在P3P74
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LPC2101FBD48数据手册
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1. General description
The LPC11U3x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11U3x operate at CPU frequencies of up to 50 MHz.
Equipped with a highly flexible and configurable full-speed USB 2.0 device controller, the
LPC11U3x brings unparalleled design flexibility and seamless integration to today’s
demanding connectivity solutions.
The peripheral complement of the LPC11U3x includes up to 128 kB of flash memory, up
to 12 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I
2
C-bus
interface, one RS-485/EIA-485 USART with support for synchronous mode and smart
card interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC,
and up to 54 general purpose I/O pins.
The I/O Handler is a software library-supported hardware engine that can be used to add
performance, connectivity and flexibility to system designs. It is available on the
LPC11U37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART,
I
2
C, and I
2
S with no or very low additional CPU load and can off-load the CPU by
performing processing-intensive functions like DMA transfers in hardware. Software
libraries for multiple I/O Handler applications are available on http://www.LPCware.com
.
For additional documentation related to the LPC11U3x parts, see Section 15
“References”.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non-Maskable Interrupt (NMI) input selectable from several input sources.
System tick timer.
Memory:
Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase
(256 byte) access.
4 kB on-chip EEPROM data memory; byte erasable and byte programmable;
on-chip API support.
Up to 12 kB SRAM data memory.
LPC11U3x
32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash; up
to 12 kB SRAM and 4 kB EEPROM; USB device; USART
Rev. 2.2 — 11 March 2014 Product data sheet
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