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MCIMX6D6AVT10ACR 其他数据使用手册 - NXP（恩智浦）
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NXP（恩智浦）
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FCBGA-624
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MCIMX6D6AVT10ACR数据手册
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NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6DQCEC
Rev. 5, 09/2017
Package Information
FCPBGA Package
21 x 21 mm, 0.8 mm pitch
NXP Reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products
Ordering Information
See Ta bl e 1
MCIMX6QxExxxxC
MCIMX6QxExxxxD
MCIMX6QxExxxxE
MCIMX6DxExxxxC
MCIMX6DxExxxxD
MCIMX6DxExxxxE
1 Introduction
The i.MX 6Dual/6Quad processors represent the latest
achievement in integrated multimedia applications
processors. These processors are part of a growing
family of multimedia-focused products that offer high
performance processing and are optimized for lowest
power consumption.
The i.MX 6Dual/6Quad processors feature advanced
implementation of the quad ARM
®
Cortex
®
-A9 core,
which operates at speeds up to 1.2 GHz. They include
2D and 3D graphics processors, 1080p video processing,
and integrated power management. Each processor
provides a 64-bit DDR3/DDR3L/LPDDR2 memory
interface and a number of other interfaces for connecting
peripherals, such as WLAN, Bluetooth
®
, GPS, hard
drive, displays, and camera sensors.
The i.MX 6Dual/6Quad processors are specifically
useful for applications such as the following:
• Netbooks (web tablets)
• Nettops (Internet desktop devices)
i.MX 6Dual/6Quad
Applications Processors for
Consumer Products
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Signal Naming Convention . . . . . . . . . . . . . . . . . . . 8
2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 19
3.2 Recommended Connections for Unused Analog
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 20
4.2 Power Supplies Requirements and Restrictions . . 33
4.3 Integrated LDO Voltage Regulator Parameters . . . 34
4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 36
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 37
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 38
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 44
4.8 Output Buffer Impedance Parameters. . . . . . . . . . 49
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 53
4.10 Multi-Mode DDR Controller (MMDC). . . . . . . . . . . 64
4.11 General-Purpose Media Interface (GPMI) Timing. 64
4.12 External Peripheral Interface Parameters . . . . . . . 73
5 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 138
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 138
5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . 139
6 Package Information and Contact Assignments . . . . . . 141
6.1 Signal Naming Convention . . . . . . . . . . . . . . . . . 141
6.2 21 x 21 mm Package Information . . . . . . . . . . . . 142
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
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