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SN74ALVC125PWR
器件3D模型
1.153
导航目录
  • 典型应用电路图在P1
  • 封装尺寸在P1P5P7P8
  • 型号编码规则在P1
  • 标记信息在P1P5P6
  • 封装信息在P1P5P6P7P8
  • 技术参数、封装参数在P2
  • 电气规格在P3
SN74ALVC125PWR数据手册
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www.ti.com
FEATURES
D, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
DESCRIPTION/ORDERING INFORMATION
1
1OE
2
1A 1Y
3
4
2OE
5
2A 2Y
6
10
3OE
9
3A 3Y
8
13
4OE
12
4A 4Y
11
SN74ALVC125
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES110H JULY 1997 REVISED SEPTEMBER 2004
Operates from 1.65 V to 3.6 V
Max t
pd
of 2.8 ns at 3.3 V
± 24-mA Output Drive at 3.3 V
Latch-up Performance Exceeds 250 mA Per
JESD 17
ESD Performance Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable ( OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube SN74ALVC125D
SOIC - D ALVC125
Tape and reel SN74ALVC125DR
SOP - NS Tape and reel SN74ALVC125NSR ALVC125
-40 ° C to 85 ° C
Tube SN74ALVC125PW
TSSOP - PW VA125
Tape and reel SN74ALVC125PWR
TVSOP - DGV Tape and reel SN74ALVC125DGVR VA125
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE A
L H H
L L L
H X Z
LOGIC DIAGRAM (POSITIVE LOGIC)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

SN74ALVC125PWR 数据手册

TI(德州仪器)
15 页 / 0.63 MByte
TI(德州仪器)
21 页 / 5.57 MByte
TI(德州仪器)
14 页 / 0.6 MByte

SN74ALVC125 数据手册

TI(德州仪器)
具有三态输出的四路总线缓冲器闸
TI(德州仪器)
四路总线缓冲器闸具有三态输出 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
TI(德州仪器)
四路总线缓冲器闸具有三态输出 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
TI(德州仪器)
74ALVC 系列,Texas Instruments高级低电压 CMOS 逻辑 工作电压:1.65 - 3.6 兼容性:输入 CMOS、输出 CMOS 按 JESD 17标准,闩锁效应性能超过 250 mA ### 74ALVC 系列
TI(德州仪器)
74ALVC 系列,Texas Instruments高级低电压 CMOS 逻辑 工作电压:1.65 - 3.6 兼容性:输入 CMOS、输出 CMOS 按 JESD 17标准,闩锁效应性能超过 250 mA ### 74ALVC 系列
TI(德州仪器)
TEXAS INSTRUMENTS  SN74ALVC125DGVR  芯片, 非反相缓冲器, TVSOP-14, 整卷
TI(德州仪器)
四路总线缓冲器闸具有三态输出 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
TI(德州仪器)
四路总线缓冲器闸具有三态输出 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
TI(德州仪器)
四路总线缓冲器闸具有三态输出 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
TI(德州仪器)
四路总线缓冲器闸具有三态输出 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
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