Datasheet 搜索 > Silicon Labs（芯科） > EFM8BB10F2A-A-QFN20R 数据手册 > EFM8BB10F2A-A-QFN20R 产品设计参考手册 4/238 页
器件3D模型￥ 8.687
EFM8BB10F2A-A-QFN20R 产品设计参考手册 - Silicon Labs（芯科）
制造商:
Silicon Labs（芯科）
封装:
QFN-20
描述:
8位微控制器 -MCU 8051 25 MHz 2 kB Flash 0.25 kB RAM 8-bit Busy Bee MCU
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
典型应用电路图在P238
原理图在P10P50P54P59P66P75P76P103P127P139P145P170
功能描述在P1P33P54P60P67P76P104P127P140P146P171P183
技术参数、封装参数在P35
应用领域在P232
型号编号列表在P35
导航目录
EFM8BB10F2A-A-QFN20R数据手册
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9.3.8 Flash Error Reset ...........................63
9.3.9 Software Reset ............................63
9.4 Reset Sources and Supply Monitor Control Registers .................64
9.4.1 RSTSRC: Reset Source .........................64
9.4.2 VDM0CN: Supply Monitor Control ......................65
10. CIP-51 Microcontroller Core ........................66
10.1 Introduction ..............................66
10.2 Features ...............................67
10.3 Functional Description ...........................67
10.3.1 Programming and Debugging Support ....................67
10.3.2 Instruction Set ............................68
10.4 CPU Core Registers ...........................72
10.4.1 DPL: Data Pointer Low .........................72
10.4.2 DPH: Data Pointer High .........................72
10.4.3 SP: Stack Pointer ...........................72
10.4.4 ACC: Accumulator ...........................73
10.4.5 B: B Register.............................73
10.4.6 PSW: Program Status Word .......................74
11. Port I/O, Crossbar, External Interrupts, and Port Match ..............75
11.1 Introduction ..............................75
11.2 Features ...............................75
11.3 Functional Description ...........................76
11.3.1 Port I/O Modes of Operation .......................76
11.3.2 Analog and Digital Functions .......................77
11.3.3 Priority Crossbar Decoder ........................79
11.3.4 INT0 and INT1 ............................82
11.3.5 Port Match .............................82
11.3.6 Direct Port I/O Access (Read/Write) .....................82
11.4 Port I/O Control Registers ..........................83
11.4.1 XBR0: Port I/O Crossbar 0 ........................83
11.4.2 XBR1: Port I/O Crossbar 1 ........................85
11.4.3 XBR2: Port I/O Crossbar 2 ........................86
11.4.4 PRTDRV: Port Drive Strength .......................87
11.4.5 P0MASK: Port 0 Mask .........................88
11.4.6 P0MAT: Port 0 Match ..........................89
11.4.7 P0: Port 0 Pin Latch ..........................90
11.4.8 P0MDIN: Port 0 Input Mode........................91
11.4.9 P0MDOUT: Port 0 Output Mode ......................92
11.4.10 P0SKIP: Port 0 Skip ..........................93
11.4.11 P1MASK: Port 1 Mask .........................94
11.4.12 P1MAT: Port 1 Match .........................95
11.4.13 P1: Port 1 Pin Latch ..........................96
11.4.14 P1MDIN: Port 1 Input Mode .......................97
11.4.15 P1MDOUT: Port 1 Output Mode ......................98
11.4.16 P1SKIP: Port 1 Skip ..........................99
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