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EP1C12F324C7N 产品设计参考手册 - Altera（阿尔特拉）
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Altera（阿尔特拉）
分类:
FPGA芯片
封装:
FBGA-324
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原理图在P20
功能描述在P44
应用领域在P7P12
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EP1C12F324C7N数据手册
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若手册格式错乱，请下载阅览PDF原文件
Figure 2: IP Upgrade Alert in Project Navigator
IP Upgrade
notification
Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required, optional, or
unsupported for IP cores in your design. You must upgrade IP cores that require upgrade before you can
compile the IP variation in the current version of the software.
The upgrade process preserves the original IP variation file in the project directory as <my_variant>_
BAK.qsys for IP targeting Arria 10 and later devices, and as <my_variant>_BAK.v, .sv, or .vhd for legacy IP
targeting 28nm devices and greater.
The upgrade process preserves the original IP variation file in the project directory as <my_variant>_
BAK.qsys.
Note:
Upgrading IP cores for Arria 10 and later devices may append a unique identifier to the original IP
core entity name(s), without similarly modifying the IP instance name. There is no requirement to
update these entity references in any supporting file; such as the Settings File (.qsf), Synopsys
Design Constraints File (.sdc), or SignalTap File (.stp), if these files contain instance names. The
software reads only the instance name and ignores the entity name in paths that specify both
names. Use only instance names in assignments.
Note: Upgrading IP cores may append a unique identifier to the original IP core entity name(s), without
similarly modifying the IP instance name. There is no requirement to update these entity
references in any supporting file; such as the Settings File (.qsf), Synopsys Design Constraints File
(.sdc), or SignalTap File (.stp), if these files contain instance names. The software reads only the
instance name and ignores the entity name in paths that specify both names. Use only instance
names in assignments.
UG-SLDVRTL
2015.11.20
Upgrading IP Cores
3
Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide
Altera Corporation
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