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P2020NSN2MHC 产品设计参考手册 - NXP(恩智浦)
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NXP(恩智浦)
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微处理器
封装:
BGA-689
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NXP P2020NSN2MHC 芯片, 微处理器, 32位, 1.2GHZ, BGA-689
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P2020NSN2MHC数据手册
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e500 Software Optimization Guide (eSOG), Rev. 0
Freescale Semiconductor 5
Preliminary—Subject to Change Without Notice
Overview
1.3 High-Level Differences
To achieve a higher frequency, both the e500 core and the MPC745x designs reduce the number of logic
levels per cycle (compared to G2 and G3 processors), which extends the pipeline. Additional resources
reduce the effect of the pipeline length on performance. These pipeline length and resource changes can
make an important difference in code scheduling. Table 1-1 lists the key microarchitectural differences
between MPC603e, MPC755, MPC745x, and e500 core processors.
Table 1-1. Microarchitectural Comparison
MPC603e MPC755 MPC745x e500 core
Pipeline
MInimum total pipeline length 4 4 7 7
Pipeline stages up to first execute 3 3 5 5
Pipeline maximum instruction throughput 2+1 branch 2+1 branch 3+1 branch 2
Instruction queue size 6 6 12 12
Completion queue size 5 6 16 14
Rename registers 5 32-bit GPR
4 FPR
6 32-bit GPR
6 FPR
1 CR
1 LR, 1 CTR
16 32-bit GPR
16 VR
16 FPR
1 CR
1 LR,1 CTR
14 64-bit GPR
14 CR
14 CA
1 LR, 1 CTR
Branch Prediction
Branch prediction structures Static prediction 64 entry BTIC
512 entry BHT
128 entry BTIC
2048 entry BHT
8 entry LS
512-entry BTB
Minimum branch mispredict penalty 1 4 6 5
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