Datasheet 搜索 > 微控制器 > TI（德州仪器） > TM4C1294NCPDTT3R 数据手册 > TM4C1294NCPDTT3R 产品设计参考手册 6/1890 页
器件3D模型￥ 93.731
TM4C1294NCPDTT3R 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
微控制器
封装:
TQFP-128
描述:
支持物联网的高性能 32 位 ARM® Cortex®-M4F MCU 128-TQFP -40 to 105
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P208P220P221P222P533P534P817P818P876P957P958P1055Hot
典型应用电路图在P74P1669
原理图在P54P81P82P83P208P533P542P600P601P679P816P817
封装尺寸在P53P79P1885P1886P1888
标记信息在P1885P1888
封装信息在P78P1885P1887P1888P1889
功能描述在P134P209P220P523P534P543P602P616P679P747P818P946
技术参数、封装参数在P536P537P1818P1835P1837P1838
应用领域在P85P688P691P970P1890
电气规格在P79P222P223P230P235P1818P1820P1822P1824P1826P1828P1830
型号编号列表在P1885
导航目录
TM4C1294NCPDTT3R数据手册
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9 Micro Direct Memory Access (μDMA) ................................................................ 678
9.1 Block Diagram ............................................................................................................ 679
9.2 Functional Description ................................................................................................. 679
9.2.1 Channel Assignments .................................................................................................. 680
9.2.2 Priority ........................................................................................................................ 681
9.2.3 Arbitration Size ............................................................................................................ 682
9.2.4 Request Types ............................................................................................................ 682
9.2.5 Channel Configuration ................................................................................................. 683
9.2.6 Transfer Modes ........................................................................................................... 685
9.2.7 Transfer Size and Increment ........................................................................................ 693
9.2.8 Peripheral Interface ..................................................................................................... 693
9.2.9 Software Request ........................................................................................................ 694
9.2.10 Interrupts and Errors .................................................................................................... 694
9.3 Initialization and Configuration ..................................................................................... 694
9.3.1 Module Initialization ..................................................................................................... 694
9.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 695
9.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 696
9.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 698
9.3.5 Configuring Channel Assignments ................................................................................ 701
9.4 Register Map .............................................................................................................. 701
9.5 μDMA Channel Control Structure ................................................................................. 702
9.6 μDMA Register Descriptions ........................................................................................ 709
10 General-Purpose Input/Outputs (GPIOs) ........................................................... 742
10.1 Signal Description ....................................................................................................... 743
10.2 Pad Capabilities .......................................................................................................... 746
10.3 Functional Description ................................................................................................. 747
10.3.1 Data Control ............................................................................................................... 748
10.3.2 Interrupt Control .......................................................................................................... 750
10.3.3 Mode Control .............................................................................................................. 751
10.3.4 Commit Control ........................................................................................................... 752
10.3.5 Pad Control ................................................................................................................. 752
10.3.6 Identification ............................................................................................................... 753
10.4 Initialization and Configuration ..................................................................................... 753
10.5 Register Map .............................................................................................................. 755
10.6 Register Descriptions .................................................................................................. 758
11 External Peripheral Interface (EPI) ..................................................................... 815
11.1 EPI Block Diagram ...................................................................................................... 816
11.2 Signal Description ....................................................................................................... 817
11.3 Functional Description ................................................................................................. 818
11.3.1 Master Access to EPI .................................................................................................. 819
11.3.2 Non-Blocking Reads .................................................................................................... 819
11.3.3 DMA Operation ........................................................................................................... 820
11.4 Initialization and Configuration ..................................................................................... 821
11.4.1 EPI Interface Options .................................................................................................. 822
11.4.2 SDRAM Mode ............................................................................................................. 822
11.4.3 Host Bus Mode ........................................................................................................... 826
11.4.4 General-Purpose Mode ............................................................................................... 847
11.5 Register Map .............................................................................................................. 854
June 18, 20146
Texas Instruments-Production Data
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