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TPS70933DBVR 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
稳压芯片
封装:
SOT-23-5
描述:
TEXAS INSTRUMENTS TPS70933DBVR 芯片, 稳压器, LDO, 固定, 0.15A, 3.3V, SOT-23-5 新
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TPS70933DBVR数据手册
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J1
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U1
Thermal Guidelines and Layout Recommendations
www.ti.com
5 Thermal Guidelines and Layout Recommendations
Thermal management is a key component in the design of any power converter and is especially
important when the power dissipation in the LDO is high. Use the following formula to approximate the
maximum power dissipation for the ambient temperature:
T
J
= T
A
+ P
D
× θ
JA
Where T
J
is the junction temperature, T
A
is the ambient temperature, P
D
is the power dissipation in the
device (Watts), and θ
JA
is the thermal resistance from junction to ambient. All temperatures are in degrees
Celsius. The maximum operating junction temperature, T
J
, must not be allowed to exceed 125°C. The
layout design must be copper trace and plane areas smartly, as thermal sinks, in order to not allow T
J
to
exceed the absolute maximum rating under all temperature and voltage conditions across the part.
Table 1 repeats information from the Dissipation Ratings Table of the TPS709xx-series datasheet for
comparison with the thermal resistance, θ
JA
, for High-K JEDEC standard boards. The maximum input
voltage can be calculated for full loads at different ambient temperatures. The input voltage must be less
than these values in order to maintain a safe junction temperature.
Table 1. Thermal Resistance, θ
JA
, and Maximum Power Dissipation
Board Package θ
JA
Max V
IN
@ 150 mA (TA = 25°C) Max V
IN
@ 150 mA (T
A
= 70°C)
High-K DBV 212°C/W 6.4 V 5.0 V
6 Board Layout
Figure 6. TPS709xxEVM-110 Assembly Layer
Figure 7. TPS709xxEVM-110 Top Layer Routing
6
TPS709xxEVM-110 Evaluation Module SLVU689A–June 2011–Revised September 2012
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