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器件3D模型￥ 72.485
XIO2000ZZZ 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
PCIe桥
封装:
LFBGA-201
Pictures:
3D模型
符号图
焊盘图
引脚图
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原理图在P23P27
应用领域在P32
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XIO2000ZZZ数据手册
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SCPU027C
3
XIO2000A Implementation Guide
1 XIO2000A Typical System Implementation
Figure 1 represents a typical implementation of the XIO2000A PCI Express to PCI translation
bridge. The device serves as a bridge between an upstream PCI Express device and up to six
downstream PCI bus devices. The XIO2000A operates only with the PCI Express interface as
the primary bus and the PCI bus interface as the secondary bus. The PCI bus interface is 32 bits
wide and operates at either 33 MHz or 66 MHz.
Figure 1. Typical System Integration
PCI Express
reference
clock
GPIO
interface
Miscellaneous
PCI bus functions
CLK_RUN, PWR_OVRD,
LOCK, M66EN, PME,
SERIRQ, and
EXTERNAL ARBITER
XIO2000A
Upstream PCI
Express
device
Auxiliary
power
(VAUX)
System-side
XIO2000A-side
PCI Express link
PCI bus
Serial
EEPROM
Either a common differential 100-MHz PCI Express reference clock or an asynchronous
single-ended 125-MHz reference clock is supported. Figure 1 illustrates the common 100-MHz
reference clock option.
If V
AUX
power states are a system requirement, the XIO2000A maintains system configuration
information in “sticky” register bits.
The EEPROM can set various configuration registers but is not necessary if those registers are
settable via software/BIOS for the system.
The serial IRQ bus passes ISA-style legacy interrupts upstream to the system host controller.
Some PCI devices require ISA-style legacy interrupts to function properly. The XIO2000A
converts serial bus IRQs into PCI Express upstream MSI messages.
Up to eight general-purpose inputs/outputs (GPIOs) exist for further system customization.
Options exist for the clock run, LOCK
, PME, M66 enable, external arbiter, and power override
features, if any of the PCI bus devices require these features.
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