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EP1K100QC208-3N 用户编程技术手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
QFP-208
描述:
可编程逻辑器件(CPLD/FPGA) EP1K100QC208-3N QFP-208
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EP1K100QC208-3N数据手册
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Altera Corporation 5
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
Table 5 shows ACEX 1K device performance for more complex designs.
These designs are available as Altera MegaCore
TM
functions.
Each ACEX 1K device contains an embedded array and a logic array. The
embedded array is used to implement a variety of memory functions or
complex logic functions, such as digital signal processing (DSP), wide
data-path manipulation, microcontroller applications, and data-
transformation functions. The logic array performs the same function as
the sea-of-gates in the gate array and is used to implement general logic
such as counters, adders, state machines, and multiplexers. The
combination of embedded and logic arrays provides the high
performance and high density of embedded gate arrays, enabling
designers to implement an entire system on a single device.
ACEX 1K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers EPC16, EPC2, EPC1, and EPC1441 configuration devices,
which configure ACEX 1K devices via a serial data stream. Configuration
data can also be downloaded from system RAM or via the Altera
MasterBlaster
TM
, ByteBlasterMV
TM
, or BitBlaster
TM
download cables. After
an ACEX 1K device has been configured, it can be reconfigured in-circuit
by resetting the device and loading new data. Because reconfiguration
requires less than 40 ms, real-time changes can be made during system
operation.
ACEX 1K devices contain an interface that permits microprocessors to
configure ACEX 1K devices serially or in parallel, and synchronously or
asynchronously. The interface also enables microprocessors to treat an
ACEX 1K device as memory and configure it by writing to a virtual
memory location, simplifying device reconfiguration.
Table 5. ACEX 1K Device Performance for Complex Designs
Application LEs
Used
Performance
Speed Grade Units
-1 -2 -3
16-bit, 8-tap parallel finite impulse response (FIR)
filter
597 192 156 116 MSPS
8-bit, 512-point Fast Fourier transform (FFT)
function
1,854 23.4 28.7 38.9
µs
113 92 68 MHz
a16450 universal asynchronous
receiver/transmitter (UART)
342 36 28 20.5 MHz
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