Datasheet 搜索 > FET驱动器 > ST Microelectronics（意法半导体） > VN7050AJTR 数据手册 > VN7050AJTR 开发手册 2/55 页
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VN7050AJTR 开发手册 - ST Microelectronics（意法半导体）
制造商:
ST Microelectronics（意法半导体）
分类:
FET驱动器
封装:
PowerSSO-16
描述:
VN7050AJ 系列 28 V 50 mOhm 高边 驱动器 带多路检测 模拟反馈
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P7Hot
原理图在P7P8
封装尺寸在P44P45P46P47P48P49P50P51P52
标记信息在P51P52
封装信息在P47P49P53
技术参数、封装参数在P9
应用领域在P1
电气规格在P9P10P11P12P13P14P15P16P17P18P19P20
导航目录
VN7050AJTR数据手册
Page:
of 55 Go
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Contents
VN7050AJ, VN7050AS
Contents
1 Block diagram and pin description ................................................ 7
2 Electrical specification .................................................................... 9
2.1 Absolute maximum ratings ................................................................ 9
2.2 Thermal data ................................................................................... 10
2.3 Main electrical characteristics ......................................................... 10
2.4 Waveforms ...................................................................................... 21
2.5 Electrical characteristics curves ...................................................... 24
3 Protections..................................................................................... 28
3.1 Power limitation ............................................................................... 28
3.2 Thermal shutdown ........................................................................... 28
3.3 Current limitation ............................................................................. 28
3.4 Negative voltage clamp ................................................................... 28
4 Application information ................................................................ 29
4.1 GND protection network against reverse battery ............................. 29
4.1.1 Diode (DGND) in the ground line ..................................................... 30
4.2 Immunity against transient electrical disturbances .......................... 30
4.3 MCU I/Os protection ........................................................................ 30
4.4 Multisense - analog current sense .................................................. 31
4.4.1 Principle of Multisense signal generation ......................................... 32
4.4.2 TCASE and VCC monitor ................................................................. 34
4.4.3 Short to VCC and OFF-state open-load detection ........................... 35
5 Maximum demagnetization energy (VCC = 16 V) ........................ 37
6 Package and PCB thermal data .................................................... 38
6.1 PowerSSO-16 thermal data ............................................................ 38
6.2 SO-8 thermal data ........................................................................... 41
7 Package information ..................................................................... 44
7.1 PowerSSO-16 package information ................................................ 44
7.2 SO-8 package information .............................................................. 46
7.3 PowerSSO-16 packing information ................................................. 47
7.4 SO-8 packing information ................................................................ 49
7.5 PowerSSO-16 marking information ................................................. 51
2/55 DocID027397 Rev 1
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