Datasheet 搜索 > FPGA芯片 > Altera（阿尔特拉） > 5AGXFB3H4F35I3G 数据手册 > 5AGXFB3H4F35I3G 数据手册 2/183 页
器件3D模型￥ 18588.172
5AGXFB3H4F35I3G 数据手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
BBGA-1152
描述:
FPGA - 现场可编程门阵列
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P10P11P19P27P31Hot
技术参数、封装参数在P4P5P14P15P16P18P19P21P22P25P26P27
电气规格在P4P104
导航目录
5AGXFB3H4F35I3G数据手册
Page:
of 183 Go
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Contents
Arria V GX, GT, SX, and ST Device Datasheet.....................................................................................................1-1
Electrical Characteristics.....................................................................................................................................................................................................1-1
Operating Conditions............................................................................................................................................................................................. 1-1
Switching Characteristics................................................................................................................................................................................................. 1-23
Transceiver Performance Specifications............................................................................................................................................................ 1-23
Core Performance Specifications........................................................................................................................................................................ 1-43
Periphery Performance.........................................................................................................................................................................................1-49
HPS Specifications.................................................................................................................................................................................................1-58
Configuration Specifications............................................................................................................................................................................................1-74
POR Specifications................................................................................................................................................................................................ 1-74
FPGA JTAG Configuration Timing....................................................................................................................................................................1-75
FPP Configuration Timing...................................................................................................................................................................................1-75
AS Configuration Timing.....................................................................................................................................................................................1-79
DCLK Frequency Specification in the AS Configuration Scheme..................................................................................................................1-80
PS Configuration Timing..................................................................................................................................................................................... 1-80
Initialization........................................................................................................................................................................................................... 1-81
Configuration Files................................................................................................................................................................................................1-82
Minimum Configuration Time Estimation.......................................................................................................................................................1-83
Remote System Upgrades.....................................................................................................................................................................................1-84
User Watchdog Internal Oscillator Frequency Specifications........................................................................................................................1-84
I/O Timing..........................................................................................................................................................................................................................1-84
Programmable IOE Delay.................................................................................................................................................................................... 1-85
Programmable Output Buffer Delay...................................................................................................................................................................1-86
Glossary...............................................................................................................................................................................................................................1-86
Document Revision History.............................................................................................................................................................................................1-93
Arria V GZ Device Datasheet................................................................................................................................ 2-1
Electrical Characteristics.....................................................................................................................................................................................................2-1
TOC-2
Altera Corporation
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