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5M160ZE64C5N 数据手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
CPLD芯片
封装:
QFP-64
描述:
ALTERA 5M160ZE64C5N 可编程逻辑芯片, CPLD, MAX V系列, 160 LE, 64EQFP
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引脚图在P118P128P140P150Hot
典型应用电路图在P13P20P21P22P23P24P25P128
原理图在P14
型号编码规则在P9
功能描述在P13P14P15P105P107P108P109P110P111
技术参数、封装参数在P44P49P51P53P54P55P56P58P59P60P61P62
电气规格在P44P49P51P52
型号编号列表在P49
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5M160ZE64C5N数据手册
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7–24 Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
MAX V Device Handbook January 2011 Altera Corporation
The Quartus II software supports both the Base mode (uses 8-bit address and data)
and the Extended mode (uses 16-bit address and data). Base mode uses only UFM
sector 0 (2,048 bits), while Extended mode uses both UFM sector 0 and sector 1 (8,192
bits). There are only four pins in SPI:
SI
,
SO
,
SCK
, and
nCS
. Table 7–9 describes the SPI
pins and functions.
Data transmitted to the
SI
port of the slave device is sampled by the slave device at
the positive
SCK
clock. Data transmits from the slave device through
SO
at the negative
SCK
clock edge. When
nCS
is asserted, it means the current device is being selected by
the master device from the other end of the SPI bus for service. When
nCS
is not
asserted, the
SI
and
SCK
ports should be blocked from receiving signals from the
master device, and
SO
should be in High Impedance state to avoid causing contention
on the shared SPI bus. All instructions, addresses, and data are transferred with the
MSB first and start with high-to-low
nCS
transition. The circuit diagram is shown in
Figure 7–20.
Table 7–9. SPI Interface Signals
Pin Description Function
SI
Serial Data Input Receive data serially.
SO
Serial Data Output Transmit data serially.
SCK
Serial Data Clock
The clock signal produced from the master device to
synchronize the data transfer.
nCS
Chip Select
Active low signal that enables the slave device to
receive or transfer data from the master device.
Figure 7–20. Circuit Diagram for SPI Interface Read or Write Operations
Read, Write, and Erase
State Machine
Op-Code Decoder
Eight-Bit Status Shift Register
Address and Data Hub
UFM Block
SPI Interface
Control Logic
SI SO SCK nCS
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