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74LVC161284DLRG4
器件3D模型
5.844
导航目录
  • 封装尺寸在P2P9P10P11
  • 型号编码规则在P2
  • 标记信息在P2
  • 封装信息在P2P9P10P11
  • 技术参数、封装参数在P1
  • 应用领域在P13
  • 电气规格在P1
74LVC161284DLRG4数据手册
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PACKAGE PREVIEW
PACKAGE PREVIEW

  
SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG Tape and reel SN74LVC161284DGGR
SSOP – DL
Tape SN74LVC161284DL
LVC161284
0°C to 70°C
SSOP – DL
Tape and reel SN74LVC161284DLR
LVC161284
0
°
C to 70
°
C
TSSOP – DGG Tape and reel 74LVC161284DGGRG4
SSOP – DL
Tape 74LVC161284DLRE4
LVC161284
SSOP – DL
Tape and reel 74LVC161284DLRG4
LVC161284
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUT
MODE
DIR
HD
OUTPUT MODE
L
L
Open drain A9−A13 to Y9−Y13 and PERI LOGIC IN to PERI LOGIC OUT
L L
Totem pole
B1−B8 to A1−A8 and C14−C17 to A14−A17
L H Totem pole B1−B8 to A1−A8, A9−A13 to Y9−Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14−C17 to A14−A17
H
L
Open drain A1−A8 to B1−B8, A9−A13 to Y9−Y13, and PERI LOGIC IN to PERI LOGIC OUT
H L
Totem pole
C14−C17 to A14−A17
H H Totem pole A1−A8 to B1−B8, A9−A13 to Y9−Y13, C14−C17 to A14−A17, and PERI LOGIC IN to PERI LOGIC OUT

74LVC161284DLRG4 数据手册

TI(德州仪器)
13 页 / 0.33 MByte
TI(德州仪器)
11 页 / 0.42 MByte
TI(德州仪器)
6 页 / 0.17 MByte

74LVC161284 数据手册

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ST Microelectronics(意法半导体)
STMICROELECTRONICS  74LVC161284TTR  芯片, 逻辑电路 - 收发器, IEEE1284
TI(德州仪器)
19位总线接口 19-BIT BUS INTERFACE
TI(德州仪器)
19位总线接口 19-BIT BUS INTERFACE
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