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74LVC161PW,118 数据手册 - Nexperia（安世）
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Nexperia（安世）
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TSSOP-16
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74LVC161PW,118数据手册
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74LVC161 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 30 September 2013 2 of 22
NXP Semiconductors
74LVC161
Presettable synchronous 4-bit binary counter; asynchronous reset
JESD8-C/JESD36 (2.7 V to 3.6 V)
Specified from 40 C to +85 C and 40 C to +125 C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC161D 40 Cto+125C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74LVC161DB 40 Cto+125C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74LVC161PW 40 Cto+125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74LVC161BQ 40 Cto+125C DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna905
Q0
Q1
CP
Q2
Q3
TC
3
4
2
5
6
9
14
13
15
12
11
MR
1
CEP
7
CET
10
D0
D1
D2
D3
PE
mna906
15
11
12
3
4
5
6
14
13
7
10
G3
1
R
9
M1
G4
2
C2/1,3,4+
1,2D
4 CT = 15
CTR4
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