Datasheet 搜索 > 放大器、缓冲器 > ADI（亚德诺） > AD210AN 数据手册 > AD210AN 数据手册 3/8 页
器件3D模型￥ 1622.058
AD210AN 数据手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
分类:
放大器、缓冲器
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PDIP-12
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AD210AN数据手册
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AD210
REV. A
–3–
INSIDE THE AD210
The AD210 basic block diagram is illustrated in Figure 1.
A +15 V supply is connected to the power port, and
±15 V isolated power is supplied to both the input and
output ports via a 50 kHz carrier frequency. The uncom-
mitted input amplifier can be used to supply gain or buff-
ering of input signals to the AD210. The fullwave
modulator translates the signal to the carrier frequency for
application to transformer T1. The synchronous demodu-
lator in the output port reconstructs the input signal. A
20 kHz, three-pole filter is employed to minimize output
noise and ripple. Finally, an output buffer provides a low
impedance output capable of driving a 2 kΩ load.
INPUT
POWER
SUPPLY
19
14
15
16
17
18
V
O
30
29
T2
POWER
POWER
OSCILLATOR
INPUT OUTPUT
MOD
DEMOD
FILTER
1
2
OUTPUT
POWER
SUPPLY
3
4
O
COM
+V
OSS
–V
OSS
AD210
PWR COMPWR
T3
T1
–V
ISS
+V
ISS
I
COM
+IN
–IN
FB
Figure 1. AD210 Block Diagram
USING THE AD210
The AD210 is very simple to apply in a wide range of ap-
plications. Powered by a single +15 V power supply, the
AD210 will provide outstanding performance when used
as an input or output isolator, in single and multichannel
configurations.
Input Configurations: The basic unity gain configura-
tion for signals up to ±10 V is shown in Figure 2. Addi-
tional input amplifier variations are shown in the following
figures. For smaller signal levels Figure 3 shows how to
obtain gain while maintaining a very high input impedance.
19
14
15
16
17
18
V
OUT
(±10V)
30
29
+V
OSS
V
SIG
±10V
AD210
+V
ISS
–V
ISS
+15V
2
3
4
–V
OSS
1
V
OUT
Figure 2. Basic Unity Gain Configuration
The high input impedance of the circuits in Figures 2 and
3 can be maintained in an inverting application. Since the
AD210 is a three-port isolator, either the input leads or
the output leads may be interchanged to create the signal
inversion.
19
14
15
16
17
18
30
29
+V
OSS
V
SIG
AD210
+V
ISS
–V
ISS
+15V
2
3
4
–V
OSS
1
V
OUT
= V
SIG
1+
( )
R
F
R
G
R
G
R
F
Figure 3. Input Configuration for G > 1
Figure 4 shows how to accommodate current inputs or sum cur-
rents or voltages. This circuit configuration can also be used for
signals greater than ±10 V. For example, a ±100 V input span
can be handled with R
F
= 20 kΩ and R
S1
= 200 kΩ.
19
14
15
16
17
18
30
29
+V
OSS
AD210
+V
ISS
–V
ISS
+15V
2
3
4
–V
OSS
1
R
S1
I
S
V
S2
V
S1
R
S2
R
F
V
OUT
V
OUT
= –R
F
V
S1
R
S1
( )
V
S2
R
S2
+
+ I
S
+ ...
Figure 4. Summing or Current Input Configuration
Adjustments
When gain and offset adjustments are required, the actual cir-
cuit adjustment components will depend on the choice of input
configuration and whether the adjustments are to be made at
the isolator’s input or output. Adjustments on the output side
might be used when potentiometers on the input side would
represent a hazard due to the presence of high common-mode
voltage during adjustment. Offset adjustments are best done at
the input side, as it is better to null the offset ahead of the gain.
Figure 5 shows the input adjustment circuit for use when the in-
put amplifier is configured in the noninverting mode. This offset
adjustment circuit injects a small voltage in series with the
19
15
16
17
18
30
29
+V
OSS
AD210
+V
ISS
–V
ISS
+15V
2
3
4
–V
OSS
R
G
HI
V
OUT
V
SIG
14
200Ω
47.5kΩ
5kΩ
100kΩ
50kΩ
LO
GAIN
OFFSET
1
Figure 5. Adjustments for Noninverting Input
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