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AD5383BST-5
器件3D模型
0
导航目录
  • 引脚图在P14
  • 原理图在P1
  • 封装尺寸在P37
  • 型号编码规则在P37
  • 焊接温度在P13
  • 功能描述在P3P14P21
  • 技术参数、封装参数在P1P4P6P13
  • 应用领域在P1
  • 电气规格在P18
AD5383BST-5数据手册
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AD5383
Rev. A | Page 17 of 40
TERMINOLOGY
Relative Accuracy
Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error, and is
expressed in LSB.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register. Ideally, with all 0s loaded to
the DAC and m = all 1s, c = 2
n – 1
V
OUT(Zero-Scale)
= 0 V
Zero-scale error is a measure of the difference between V
OUT
(actual) and V
OUT
(ideal), expressed in mV. It is mainly due to
offsets in the output amplifier.
Offset Error
Offset error is a measure of the difference between V
OUT
(actual)
and V
OUT
(ideal) in the linear region of the transfer function,
expressed in mV. Offset error is measured on the AD5383-5
with Code 32 loaded into the DAC register, and on the
AD5383-3 with Code 64.
Gain Error
Gain Error is specified in the linear region of the output range
between V
OUT
= 10 mV and V
OUT
= AV
DD
– 50 mV. It is the
deviation in slope of the DAC transfer characteristic from the
ideal and is expressed in %FSR with the DAC output unloaded.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC at
midscale in response to a full-scale code (all 0s to all 1s, and
vice versa) and output change of all other DACs. It is expressed
in LSB.
DC Output Impedance
DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change, and is measured from the
BUSY
rising
edge.
Digital-to-Analog Glitch Energy
Digital-to-analog glitch energy is the amount of energy injected
into the analog output at the major code transition. It is
specified as the area of the glitch in nV-s. It is measured by
toggling the DAC register data between 0x1FFF and 0x2000.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one DAC due to both the digital change and to the
subsequent analog output change at another DAC. The victim
channel is loaded with midscale. DAC-to-DAC crosstalk is
specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter is
defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the devices digital inputs can be capacitively coupled both
across and through the device to show up as noise on the V
OUT
pins. It can also be coupled along the supply and ground lines.
This noise is digital feedthrough.
Output Noise Spectral Density
Output noise spectral density is a measure of internally
generated random noise. Random noise is characterized as a
spectral density (voltage per √Hertz). It is measured by loading
all DACs to midscale and measuring noise at the output. It is
measured in nV/√Hz in a 1 Hz bandwidth at 10 kHz.

AD5383BST-5 数据手册

ADI(亚德诺)
40 页 / 1.17 MByte

AD5383 数据手册

ADI(亚德诺)
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32通道, 14位,并行和串行输入,双极性电压输出DAC 32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC
ADI(亚德诺)
32通道, 14位,并行和串行输入,双极性电压输出DAC 32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC
ADI(亚德诺)
32通道, 3 V / 5 V单电源, 12位电压输出DAC 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
ADI(亚德诺)
32通道, 3 V / 5 V单电源, 12位电压输出DAC 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
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