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AD7686BRMZ 数据手册 - ADI（亚德诺）
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ADI（亚德诺）
分类:
AD转换器
封装:
MSOP-10
描述:
ANALOG DEVICES AD7686BRMZ 模数转换器, SAR, 16 bit, 500 kSPS, 单, 1.8 V, 5.8 V, MSOP
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AD7686BRMZ数据手册
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AD7686 Data Sheet
THEORY OF OPERATION
SW+MSB
16,384C
IN+
LSB
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
IN–
4C 2C C C32,768C
SW–MSB
16,384C
LSB
4C 2C C C32,768C
02969-024
Figure 24. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7686 is a fast, low power, single-supply, precise 16-bit
ADC using a successive approximation architecture.
The AD7686 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
For example, when operating at 100 SPS, the device consumes
3.75 µW typically, which is ideal for battery-powered
applications.
The AD7686 provides the user with on-chip, track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7686 is specified from 4.5 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or a tiny 10-lead LFCSP that
combines space savings and allows flexible configurations.
This device is pin-for-pin-compatible with the AD7685,
AD7687, and AD7688.
CONVERTER OPERATION
The AD7686 is a successive approximation ADC based on a
charge redistribution DAC. Figure 24 shows a simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is complete and the CNV input goes high,
a conversion phase initiates. When the conversion phase begins,
SW+ and SW− are opened first.
The two capacitor arrays are then disconnected from the inputs
and connected to the GND input. Therefore, the differential
voltage between the inputs IN+ and IN−, captured at the end of
the acquisition phase, is applied to the comparator inputs,
causing the comparator to become unbalanced.
By switching each element of the capacitor array between GND
and REF, the comparator input varies by binary weighted
voltage steps (V
REF
/2, V
REF
/4 . . . V
REF
/65536). The control logic
toggles these switches, starting with the MSB, to bring the
comparator back into a balanced condition. After the
completion of this process, the part returns to the acquisition
phase and the control logic generates the ADC output code and
a busy signal indicator. Because the AD7686 has an on-board
conversion clock, the serial clock, SCK, is not required for the
conversion process.
Rev. C | Page 12 of 28
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