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AD8155-EVALZ 数据手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
描述:
6.5 Gbps的双缓冲复用器/解复用器 6.5 Gbps Dual Buffer Mux/Demux
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
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引脚图在P7P35Hot
典型应用电路图在P18
原理图在P1P22
封装尺寸在P35
型号编码规则在P30P35
功能描述在P1P7P35
技术参数、封装参数在P1P3P5P6
应用领域在P1P8P18P20P22P23P26
电气规格在P9
导航目录
AD8155-EVALZ数据手册
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of 36 Go
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AD8155
Rev. 0 | Page 3 of 36
SPECIFICATIONS
V
CC
= V
TTI
= V
TTO
= 1.8 V, DV
CC
= 3.3 V, V
EE
= 0 V, R
L
= 50 Ω, basic configuration
1
, data rate = 6.5 Gbps, data pattern = PRBS7, ac-
coupled inputs and outputs, differential input swing = 800 mV p-p, T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
Data Rate/Channel (NRZ) DC 6.5 Gbps
Deterministic Jitter (No
Channel)
Data rate = 6.5 Gbps, EQ setting = 0 22 ps p-p
Random Jitter (No Channel) RMS, data rate = 6.5 Gbps 1 ps
Residual Deterministic Jitter
with Receive Equalization
Data rate 6.5 Gbps, 20 inch FR4 30 ps p-p
Data rate 6.5 Gbps, 40 inch FR4 40 ps p-p
Residual Deterministic Jitter
with Transmit Preemphasis
Data rate 6.5 Gbps, 10 inch FR4 35 ps p-p
Data rate 6.5 Gbps, 30 inch FR4 42 ps p-p
Propagation Delay 50% input to 50% output (maximum EQ) 700 ps
Lane-to-Lane Skew
Signal path and switch architecture is balanced
and symmetric (maximum EQ)
90 ps
Switching Time 50% logic switching to 50% output data 150 ns
Output Rise/Fall Time 20% to 80% (PE = lowest setting) 62 ps
INPUT CHARACTERISTICS
Differential Input Voltage
Swing
V
ICM
2
= V
CC
− 0.6 V, V
CC
= V
MIN
to V
MAX
, T
A
= T
MIN
to
T
MAX
,
LOS control register = 0x05
200 2000
mV p-p
diff
Input Voltage Range Single-ended absolute voltage level, V
L
minimum V
EE
+ 0.6 V
Single-ended absolute voltage level, V
H
maximum V
CC
+ 0.3 V
OUTPUT CHARACTERISTICS
Output Voltage Swing Differential, PE = 0, default output level, @ dc 590 725 820
mV p-p
diff
Output Voltage Range, Single-
Ended Absolute Voltage Level
TX_HEADROOM = 0, V
L
minimum V
CC
− 1.1 V
TX_HEADROOM = 0, V
H
maximum V
CC
+ 0.6 V
TX_HEADROOM = 1, V
L
minimum V
CC
− 1.3 V
TX_HEADROOM = 1, V
H
maximum V
CC
+ 0.6 V
Output Current Port A/B/C, PE_A/B/C = minimum 16 mA
Port A/B/C, PE_A/B/C = 6 dB, V
OD
= 800 mV p-p 32 mA
TERMINATION CHARACTERISTICS
Resistance Differential, V
CC
= V
MIN
to V
MAX
, T
A
= T
MIN
to T
MAX
90 100 110 Ω
LOS CHARACTERISTICS
DC Assert Level 50
mV p-p
diff
DC Deassert Level 300
mV p-p
diff
LOS to Output Squelch
LOS control = 0, V
ID
= 0 to 50% OP/ON settling,
V
CC
= 1.8 V
21 ns
LOS to Output Enable
LOS control = 0, data present to first valid
transition, V
CC
= 1.8 V
67 ns
POWER SUPPLY
Operating Range
V
CC
V
EE
= 0 V, TX_HEADROOM = 0 1.6 1.8 to 3.3 3.6 V
V
EE
= 0 V, TX_HEADROOM = 1 2.2 3.3 3.6 V
DV
CC
DV
CC
≥ V
CC
, V
EE
= 0 V 1.6 1.8 to 3.3 3.6 V
V
TTI
1.2 V
CC
+ 0.3 V
V
TTO
1.2 V
CC
+ 0.3 V
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