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AD8155
Rev. 0 | Page 5 of 36
I
2
C TIMING SPECIFICATIONS
SCL
S Sr
NOTES
1. S = START CONDITION.
2. Sr = REPEAT START.
3. P = STOP.
SP
SD
A
t
F
t
LOW
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STA
t
HD;STA
t
HIGH
t
F
t
SU;STO
t
R
t
BUF
t
R
08262-002
Figure 2. I
2
C Timing Diagram
Table 2. I
2
C Timing Parameters
Parameter Symbol Min Max Unit
SCL Clock Frequency f
SCL
0 400+ kHz
Hold Time for a Start Condition t
HD;STA
0.6 μs
Setup Time for a Repeated Start Condition t
SU;STA
0.6 μs
Low Period of the SCL Clock t
LOW
1.3 μs
High Period of the SCL Clock t
HIGH
0.6 μs
Data Hold Time t
HD;DAT
0 μs
Data Setup Time t
SU;DAT
10 ns
Rise Time for Both SDA and SCL t
R
1 300 ns
Fall Time for Both SDA and SCL t
F
1 300 ns
Setup Time for Stop Condition t
SU;STO
0.6 μs
Bus Free Time Between a Stop and a Start Condition t
BUF
1 μs
Bus Free Time After a Reset 1 μs
Reset Pulse Width 10 ns
Capacitance for Each I/O Pin C
i
5 7 pF

AD8155-EVALZ 数据手册

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AD8155 数据手册

ADI(亚德诺)
6.5 Gbps的双缓冲复用器/解复用器 6.5 Gbps Dual Buffer Mux/Demux
ADI(亚德诺)
ANALOG DEVICES  AD8155ACPZ  芯片, 模拟多路复用器/信号分离器, 双路, 2:1, LFCSP-64
ADI(亚德诺)
6.5 Gbps的双缓冲复用器/解复用器 6.5 Gbps Dual Buffer Mux/Demux
ADI(亚德诺)
6.5 Gbps的双缓冲复用器/解复用器 6.5 Gbps Dual Buffer Mux/Demux
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