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ADM1166ASUZ-REEL 数据手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
分类:
电源监控芯片
封装:
TQFP-48
描述:
超序与余量控制和非易失故障记录 Super Sequencer with Margining Control and Nonvolatile Fault Recording
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ADM1166ASUZ-REEL数据手册
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ADM1166 Data Sheet
Rev. A | Page 8 of 33
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
09332-003
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
ADM1166
TOP VIEW
(Not to Scale)
GND
VDDCAP
AUX1
AUX2
SDA
SCL
A1
A0
VCCP
PDOGND
AGND
REFGND
REFIN
REFOUT
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
PDO1
NOTE
1. THIS PAD IS A NO CONNECT (NC).
IF POSSIBLE, SOLDER THIS PAD TO THE BOARD
FOR IMPROVED MECHANICAL STABILITY.
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
Figure 3. 40-Lead LFCSP Pin Configuration
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
NC
48
GND
47
VDDCAP
46
AUX1
45
AUX2
44
SDA
43
SCL
42
A1
41
A0
40
VCCP
39
PDOGN
D
38
NC
37
NC
13
AGND
14
REFGND
15
REFIN
16
REFOUT
17
DAC1
18
DAC2
19
DAC3
20
DAC4
21
DAC5
22
DAC6
23
NC
24
NC
1
V
X1
2
V
X2
3
V
X3
4
V
X4
5
V
X5
6
V
P1
7
V
P2
8
V
P3
9
V
P4
10
VH
11
NC
12
NC
36
PDO1
35
PDO2
34
PDO3
33
PDO4
32
PDO5
31
PDO6
30
PDO7
29
PDO8
28
PDO9
27
PDO10
26
NC
25
ADM1166
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
09332-004
Figure 4. 48-Lead TQFP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
40-Lead
LFCSP
48-Lead
TQFP
Mnemonic Description
N/A
1
1, 12, 13, 24,
25, 36, 37, 48
NC No Connect. Do not connect to this pin.
1 to 5 2 to 6 VX1 to VX5 (VXx)
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to
1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
6 to 9 7 to 10 VP1 to VP4 (VPx)
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the
input attenuation on a potential divider connected to these pins, the output of which
connects to a supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from
1.25 V to 3.00 V, and from 0.573 V to 1.375 V.
10 11 VH
High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the
input attenuation on a potential divider connected to this pin, the output of which connects
to a supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.
11 14 AGND
2
Ground Return for Input Attenuators.
12 15 REFGND
2
Ground Return for On-Chip Reference Circuits.
13 16 REFIN
Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage.
The on-board reference can be used by connecting the REFOUT pin to the REFIN pin.
14 17 REFOUT
Reference Output, 2.048 V. Typically connected to REFIN. Note that the capacitor must be
connected between this pin and REFGND. A 10 μF capacitor is recommended for this purpose.
15 to 20 18 to 23 DAC1 to DAC6 Voltage Output DACs. These pins default to high impedance at power-up.
21 to 30 26 to 35 PDO10 to PDO1 Programmable Driver Outputs.
31 38 PDOGND
2
Ground Return for Driver Outputs.
32 39 VCCP
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between
this pin and GND. A 10 μF capacitor is recommended for this purpose.
33 40 A0 Logic Input. This pin sets the seventh bit of the SMBus interface address.
34 41 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address.
35 42 SCL SMBus Clock Pin. Bidirectional, open-drain pin that requires external resistive pull-up.
36 43 SDA SMBus Data Pin. Bidirectional, open-drain pin that requires external resistive pull-up.
37, 38 44, 45 AUX2, AUX1 Auxiliary, Single-Ended ADC Inputs.
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