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ATMEGA8515L-8AU 数据手册 - Microchip（微芯）
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Microchip（微芯）
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微控制器
封装:
TQFP-44
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引脚图在P2P5P61P97Hot
原理图在P3P8P59P80P81P82P84P98P103P104P106P108
封装尺寸在P245P246P247P248
型号编码规则在P244
封装信息在P245P251
应用领域在P31P45P54P57P166P169P179P180
电气规格在P59P251
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ATMEGA8515L-8AU数据手册
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59
ATmega8515(L)
2512J–AVR–10/06
I/O Ports
Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital
I/O ports. This means that the direction of one port pin can be changed without uninten-
tionally changing the direction of any other pin with the SBI and CBI instructions. The
same applies when changing drive value (if configured as output) or enabling/disabling
of pull-up resistors (if configured as input). Each output buffer has symmetrical drive
characteristics with both high sink and source capability. The pin driver is strong enough
to drive LED displays directly. All port pins have individually selectable pull-up resistors
with a supply-voltage invariant resistance. All I/O pins have protection diodes to both
V
CC
and Ground as indicated in Figure 29. Refer to “Electrical Characteristics” on page
197 for a complete list of parameters.
Figure 29. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case
“x” represents the numbering letter for the port, and a lower case “n” represents the bit
number. However, when using the register or bit defines in a program, the precise form
must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally
as PORTxn. The physical I/O Registers and bit locations are listed in “Register Descrip-
tion for I/O Ports” on page 75.
Three I/O memory address locations are allocated for each port, one each for the Data
Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The
Port Input Pins I/O location is read only, while the Data Register and the Data Direction
Register are read/write. In addition, the Pull-up Disable – PUD bit in SFIOR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on
page 60. Most port pins are multiplexed with alternate functions for the peripheral fea-
tures on the device. How each alternate function interferes with the port pin is described
in “Alternate Port Functions” on page 64. Refer to the individual module sections for a
full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use
of the other pins in the port as general digital I/O.
C
pin
Logic
R
pu
See Figure
"General Digital I/O" fo
r
Details
Pxn
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