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ATSENSE301HA-AUR 数据手册 - ATMEL（爱特美尔）
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ATSENSE301HA-AUR数据手册
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8
ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET]
11219B–ATSENSE–20-Feb-14
2.2 ATSENSE-101
Figure 2-2. 20-lead SOIC Package
ATSENSE-101
1
NPCS
2 3 4 5 6 7 8 9 10
MCLK
VDDT
VDDIN
VP1
VN
VREF
GNDREF
GNDA
VDDA
IN1 IP1
20
MISO
19
MOSI
18
SPCK
17
ITOUT
20
GNDD
16 19
VDDIO
15 1814 1713
IP0
12 11
IN0
Table 2-2. ATSENSE-101 Pin Description
Pin Name I/O Pin Number Type Function
MCLK Input 1 Digital Master clock Input
VDDT Input 2 Power Pin reserved for test. Connect to VDDIN / VDDIO plane
VDDIN Input 3 Power 2.8V LDO Power supply input pin
VP1 Input 4 Analog Voltage channel 1, positive input
VN Input 5 Analog Voltage channel negative input
VREF In / Out 6 Analog
Voltage reference output and ADCs reference buffer
input
GNDREF Ground 7 Ground Voltage reference ground pin
GNDA Ground 8 Ground
Ground pin for low noise analog circuits and low noise
negative ADC reference
VDDA In / Out 9 Analog 2.8V LDO output and analog circuits power supply input
IN1 Input 10 Analog Current channel 1, negative input
IP1 Input 11 Analog Current channel 1, positive input
IN0 Input 12 Analog Current channel 0 (Tamper), negative input
IP0 Input 13 Analog Current channel 0 (Tamper), positive input
MOSI Input 14 Digital SPI port: master output slave input
SPCK Input 15 Digital SPI port: serial clock
ITOUT Output 16 Digital Interrupt output line. open drain
VDDIO Input 17 Power
Power supply input pin for digital I/O and digital core
circuits
GNDD Ground 18 Ground Ground pin for digital I/O and digital core circuits
MISO Output 19 Digital SPI port: master input slave output
NPCS Input 20 Digital SPI port: active-low chip select
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