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CD74HCT166数据手册
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Data sheet acquired from Harris Semiconductor
SCHS157C
Features
Buffered Inputs
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
Pinout
CD54HC166, CD54HCT166
(CERDIP)
CD74HC166, CD74HCT166
(PDIP, SOIC)
TOP VIEW
Description
The ’HC166 and ’HCT166 8-bit shift register is fabricated
with silicon gate CMOS technology. It possesses the low
power consumption of standard CMOS integrated circuits,
and can operate at speeds comparable to the equivalent low
power Schottky device.
The ’HCT166 is functionally and pin compatible with the
standard ’LS166.
The 166 is an 8-bit shift register that has fully synchronous
serial or parallel data entry selected by an active LOW Parallel
Enable (
PE) input. When the PE is LOW one setup time before
the LOW-to-HIGH clock transition, parallel data is entered into
the register. When
PE is HIGH, data is entered into the internal
bit position Q0 from Serial Data Input (DS), and the remaining
bits are shifted one place to the right (Q0 Q1 Q2, etc.)
with each positive-going clock transition. For expansion of the
register in parallel to serial converters, the Q7 output is con-
nected to the DS input of the succeeding stage.
The clock input is a gated OR structure which allows one
input to be used as an active LOW Clock Enable (
CE) input.
The pin assignment for the CP and
CE inputs is arbitrary and
can be reversed for layout convenience. The LOW-to-HIGH
transition of
CE input should only take place while the CP is
HIGH for predictable operation.
A LOW on the Master Reset (
MR) input overrides all other
inputs and clears the register asynchronously, forcing all bit
positions to a LOW state.
Ordering Information
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
DS
D0
D1
D2
D3
CE
GND
CP
V
CC
D7
Q7
D6
D5
D4
MR
PE
PART NUMBER TEMP. RANGE (
o
C) PACKAGE
CD54HC166F3A -55 to 125 16 Ld CERDIP
CD54HCT166F3A -55 to 125 16 Ld CERDIP
CD74HC166E -55 to 125 16 Ld PDIP
CD74HC166M -55 to 125 16 Ld SOIC
CD74HC166MT -55 to 125 16 Ld SOIC
CD74HC166M96 -55 to 125 16 Ld SOIC
CD74HCT166E -55 to 125 16 Ld PDIP
CD74HCT166M -55 to 125 16 Ld SOIC
CD74HCT166MT -55 to 125 16 Ld SOIC
CD74HCT166M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC166, CD74HC166,
CD54HCT166, CD74HCT166
High-Speed CMOS Logic
8-Bit Parallel-In/Serial-Out Shift Register
[
/Title
(
CD74
H
C166
,
C
D74
H
CT16
6
)
/
Sub-
j
ect
(
High
S
peed
C
MOS
L
ogic
8
-Bit
P
aral-
l
el-
I
n/Seri

CD74HCT166 数据手册

TI(德州仪器)
16 页 / 0.44 MByte

CD74 数据手册

TI(德州仪器)
TEXAS INSTRUMENTS  CD74HC4052M96  芯片, 模拟多路复用器/信号分离器, 双路, 4:1, SOIC-16
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TEXAS INSTRUMENTS  CD74HC4051PWR  芯片, 74HC 逻辑器件
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74HC4000 系列,Texas Instruments标准逻辑 IC 使用 CMOS 技术,以达到与 LSTTL 相似的工作速度,具有低 CMOS 集成电路功耗。 74HC4000 逻辑系列是与标准 LS 逻辑系列功能和引脚兼容,且所有设备具有驱动 10 LSTTL 负载的功能。广泛的电压范围:2 - 6 直流 ### 74HC 系列
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TEXAS INSTRUMENTS  CD74HC4051M  芯片, 74HC CMOS逻辑器件
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TEXAS INSTRUMENTS  CD74HC4051M96  芯片, 模拟多路复用器/分离器, 8X1, SOIC-16, 整卷
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TEXAS INSTRUMENTS  CD74HC4051E  芯片, 模拟多路复用器/分离器, 8 X 1, DIP-16
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TI(德州仪器)
74HC4000 系列,Texas Instruments标准逻辑 IC 使用 CMOS 技术,以达到与 LSTTL 相似的工作速度,具有低 CMOS 集成电路功耗。 74HC4000 逻辑系列是与标准 LS 逻辑系列功能和引脚兼容,且所有设备具有驱动 10 LSTTL 负载的功能。广泛的电压范围:2 - 6 直流 ### 74HC 系列
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