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器件3D模型￥ 26.005
DAC084S085CIMM 数据手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DA转换器
封装:
VSSOP-10
描述:
TEXAS INSTRUMENTS DAC084S085CIMM 数模转换器, 四路, 8 bit, 串行, 2.7V 至 5.5V, SOP, 10 引脚
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DAC084S085CIMM数据手册
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DAC084S085
SNAS363E –MAY 2006–REVISED MARCH 2013
www.ti.com
A.C. and Timing Characteristics
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for V
A
= +2.7V to +5.5V, V
REFIN
= V
A
, C
L
= 200 pF to GND, f
SCLK
= 30 MHz, input code
range 3 to 252. Boldface limits apply for T
MIN
≤ T
A
≤ T
MAX
and all other limits are at T
A
= 25°C, unless otherwise specified.
Units
Symbol Parameter Conductions Typical
(1)
Limits
(1)
(Limits)
f
SCLK
SCLK Frequency 40 30 MHz (max)
40h to C0h code change
t
s
Output Voltage Settling Time
(2)
3 4.5 µs (max)
R
L
= 2 kΩ, C
L
= 200 pF
SR Output Slew Rate 1 V/µs
Glitch Impulse Code change from 80h to 7Fh 12 nV-sec
Digital Feedthrough 0.5 nV-sec
Digital Crosstalk 1 nV-sec
DAC-to-DAC Crosstalk 3 nV-sec
Multiplying Bandwidth V
REFIN
= 2.5V ± 0.1Vpp 160 kHz
V
REFIN
= 2.5V ± 0.1Vpp
Total Harmonic Distortion 70 dB
input frequency = 10kHz
V
A
= 3V 6 µsec
t
WU
Wake-Up Time
V
A
= 5V 39 µsec
1/f
SCLK
SCLK Cycle Time 25 33 ns (min)
t
CH
SCLK High time 7 10 ns (min)
t
CL
SCLK Low Time 7 10 ns (min)
SYNC Set-up Time prior to SCLK
t
SS
4 10 ns (min)
Falling Edge
Data Set-Up Time prior to SCLK Falling
t
DS
1.5 3.5 ns (min)
Edge
Data Hold Time after SCLK Falling
t
DH
1.5 3.5 ns (min)
Edge
t
CFSR
SCLK fall prior to rise of SYNC 0 3 ns (min)
t
SYNC
SYNC High Time 6 10 ns (min)
(1) Typical figures are at T
J
= 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing
Quality Level).
(2) This parameter is specified by design and/or characterization and is not tested in production.
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