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器件3D模型￥ 245.605
DSP56303VL100 数据手册 - Freescale（飞思卡尔）
制造商:
Freescale（飞思卡尔）
分类:
DSP数字信号处理器
封装:
BGA-196
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P1
型号编码规则在P108
封装信息在P3P67P68P70P72P74P76P78P80P82P84
技术参数、封装参数在P1P3P4P5P6P7P8P9P10P11P12P13
应用领域在P4
电气规格在P22P23P25P27P29P31P33P35P37P39P41P43
导航目录
DSP56303VL100数据手册
Page:
of 109 Go
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DSP56303 Technical Data, Rev. 11
1-2 Freescale Semiconductor
Signals/Connections
Figure 1-1. Signals Identified by Functional Group
Notes: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each of these modes is configured independently, any combination
of these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]).
Signals with dual designations (for example, HAS
/HAS) have configurable polarity.
2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals
(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
3. TIO[0–2] can be configured as GPIO signals.
4. Ground connections shown in this figure are for the TQFP package. In the MAP-BGA package, in addition to the
GND
P
and GND
P1
connections, there are 64 GND connections to a common internal package ground plane.
DSP56303
24
18
External
Address Bus
External
Data Bus
External
Bus
Control
Enhanced
Synchronous Serial
Interface Port 0
(ESSI0)
2
Timers
3
PLL
OnCE/
JTAG Port
Power Inputs:
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
A[0–17]
D[0–23]
AA0/RAS0
–
AA3/RAS3
RD
WR
TA
BR
BG
BB
CAS
BCLK
BCLK
TCK
TDI
TDO
TMS
TRST
DE
CLKOUT
PCAP
After
Reset
NMI
V
CCP
V
CCQ
V
CCA
V
CCD
V
CCC
V
CCH
V
CCS
4
Serial
Communications
Interface (SCI) Port
2
4
2
2
Grounds
4
:
PLL
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
GND
P
GND
P1
GND
Q
GND
A
GND
D
GND
C
GND
H
GND
S
4
Interrupt/
Mode Control
MODA
MODB
MODC
MODD
RESET
Host
Interface
(HI08) Port
1
Non-Multiplexed
Bus
H[0–7]
HA0
HA1
HA2
HCS/
HCS
Single DS
HRW
HDS
/HDS
Single HR
HREQ
/HREQ
HACK
/HACK
RXD
TXD
SCLK
SC0[0–2]
SCK0
SRD0
STD0
TIO0
TIO1
TIO2
8
3
4
EXTAL
XTAL
Clock
Enhanced
Synchronous Serial
Interface Port 1
(ESSI1)
2
SC1[0–2]
SCK1
SRD1
STD1
3
Multiplexed
Bus
HAD[0–7]
HAS
/HAS
HA8
HA9
HA10
Double DS
HRD
/HRD
HWR
/HWR
Double HR
HTRQ
/HTRQ
HRRQ
/HRRQ
Port B
GPIO
PB[0–7]
PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15
Port E GPIO
PE0
PE1
PE2
Port C GPIO
PC[0–2]
PC3
PC4
PC5
Port D GPIO
PD[0–2]
PD3
PD4
PD5
Timer GPIO
TIO0
TIO1
TIO2
Port A
4
IRQA
IRQB
IRQC
IRQD
PINIT
RESET
During Reset
After Reset
Reset
During
4
2
2
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