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DSPIC30F2010-20E/SOG 数据手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
SOIC
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功能描述在P91P95
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DSPIC30F2010-20E/SOG数据手册
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dsPIC30F2010
DS70118J-page 92 © 2011 Microchip Technology Inc.
15.2 Framed SPI Support
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit FRMEN enables
framed SPI support and causes the SSx
pin to perform
the frame synchronization pulse (FSYNC) function.
The control bit SPIFSD determines whether the SSx
pin is an input or an output (i.e., whether the module
receives or generates the frame synchronization
pulse). The frame pulse is an active-high pulse for a
single SPI clock cycle. When frame synchronization is
enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
FIGURE 15-1: SPI BLOCK DIAGRAM
FIGURE 15-2: SPI MASTER/SLAVE CONNECTION
Note: x = 1 or 2.
Read Write
Internal
Data Bus
SDIx
SDOx
SSx
SCKx
SPIxSR
SPIxBUF
bit 0
Shift
clock
Edge
Select
F
CY
Primary
1:1, 1:4,
Enable Master Clock
Prescaler
Secondary
Prescaler
1:1-1:8
SS and FSYNC
Control
Clock
Control
Transmit
SPIxBUF
Receive
1:16, 1:64
Serial Input Buffer
(SPIxBUF)
Shift Register
(SPIxSR)
MSb
LSb
SDOx
SDIx
PROCESSOR 1
SCKx
SPI Master
Serial Input Buffer
(SPIyBUF)
Shift Register
(SPIySR)
LSb
MSb
SDIy
SDOy
PROCESSOR 2
SCKy
SPI Slave
Serial Clock
Note: x = 1 or 2, y = 1 or 2.
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