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DSPIC30F3011-30I/P 数据手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
DIP-40
描述:
MICROCHIP DSPIC30F3011-30I/P 数字信号控制器, dsPIC30F系列, 40 MHz, 24 KB, 30 输入, I2C, SPI, UART, 5.5 V
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DSPIC30F3011-30I/P数据手册
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3
16-bit Embedded Control Solutions
Flexible Integrated Peripherals
Microchip offers a rich set of high-performance peripherals that integrate seamlessly with customer application and enable
solution with reduced costs and time. The 16-bit family offers key communication and control peripherals like SPI, UART,
CAN, PWM, Timers and I
2
C, as well as specialized peripherals for USB, graphics, motor control and digital power. With
intelligent analog peripherals, you can integrate analog functions such as high-performance ADCs, DACs and op amps into
your applications providing simple-to-use interfaces that ease analog design. In addition, core independent peripherals
such as CLC, PTG and crypto enable higher levels of integration and flexibility.
PIC24 and dsPIC33 Family Block Diagram
16-bit Core
PIC24F 16 MIPS
dsPIC33F & PIC24H 40 MIPS
dsPIC33E & PIC24E 70 MIPS
16-bit
ALU
16 × 16
Register
Barrel
Shifter
17 × 17
MPY
4 KB–512 KB
Flash
ECC
Flash
Live Update
Flash
512 B–96 KB
RAM
4 Ch.
DMA
JTAG &
EMU
Address
Generation
MEMORY BUS
PERIPHERAL BUS
ADC: 10-bit, 12-bit and16-bit options
DAC
Comparators
Op Amps
Charge Time Measurement Unit (CTMU)
Intelligent
Analog
16-bit and 32-bit Timers
Input Capture
Output Capture
16-bit PWM
Multiple-Output Capture Compare PWM (MCCP) and
Single-Outputs CCP (SCCP)
Timers/PWMs
UART with LIN and IrDA
®
SPI with I
2
S™
I
2
C™
USB: Device, Host, OTG
CAN
Peripheral Pin Select (PPS)
Parallel Master Port (PMP)
Communications
BOR, LVD, POR
WDT and Windowed WDT
Deadman Timer (DMT)
RTCC: Clock, Calendar, Alarm
CRC: Flash, RAM and Special Function Registers (SFR)
Class B Features: Illegal Opcode Detect, Error Trap Monitor,
Reset Traceability, Oscillator Lock, Fail-Safe Clock Monitor,
Frequency Check, PWM Lock
System Level
eXtreme Low Power (XLP) - Deep Sleep
VBAT
Flexible Wake-Up Sources
Low
Power
Crypto Engine with 256-bit AES and Random Number Generator (RNG)
Configurable Logic Cells (CLC)
Peripheral Trigger Generator (PTG)
Core
Independent
Peripherals
PWM with Flexible Modes, Dead-Time,
Edge or Center Alignment, Fault Inputs
ADC Triggered by PWM Modules
Quadrature Encoder Interface (QEI)
Motor
Control
ADC 4 Msps with 6 Sample & Holds
PWM with 1 ns Duty Cycle
Comparators with 25 ns speed
Digital
Power
Segmented LCD Driver: Up to 480 Segments
Graphical Display Driver: with Hardware Acceleration
Displays
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