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器件3D模型￥ 72.479
EP1C4F400C8N 数据手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
FBGA-400
描述:
可编程逻辑器件(CPLD/FPGA) EP1C4F400C8N FBGA-400
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P162P314P317P377Hot
典型应用电路图在P25P27P29P31P255P273
原理图在P22P141P341
封装尺寸在P12P117P377P383P384
型号编码规则在P11P117
功能描述在P21P148P149P150P152P336P338P340
技术参数、封装参数在P85P86P87P88P89P90P94P113P114P142P224P225
应用领域在P102P203P228
电气规格在P225
导航目录
EP1C4F400C8N数据手册
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6–40 Altera Corporation
Preliminary May 2008
Cyclone Device Handbook, Volume 1
Dedicated Clock Input Pins
Cyclone FPGAs have up to four dedicated clock input pins (CLK[3..0],
two on the left and right side of the device. You can use the CLK[3..0]
pins to drive the PLLs, or directly drive them onto the global clock
network. Table 6–17 shows which clock pins drive which global clock
network.
Dual-Purpose Clock I/O Pins
Cyclone FPGAs can have up to eight dual-purpose clock pins,
DPCLK[7..0] (two on each side of the device). These dual-purpose pins
can connect to the global clock network. You can use the DPCLK[7..0]
pins for high fanout control signals, such as asynchronous clears, presets,
clock enables, or protocol control signals (e.g., TRDY and IRDY for PCI, or
DQS signals for external memory interfaces). These pins are also available
as general-purpose I/O pins, meaning they can be inputs, outputs, or
bidirectional pins. Table 6–18 shows which dual-purpose clock pins drive
which global clock network in Cyclone FPGAs.
Table 6–17. Dedicated Clock Input Pin Connections to Global Clock Network
Clock
Input Pin
GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7
CLK0
v
—
v
—————
CLK1 (1)
—
v
—
v
————
CLK2
————
v
—
v
—
CLK3 (1)
—————
v
—
v
Note to Table 6–17:
(1) The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3.
Table 6–18. Dual-Purpose Clock I/O Connections to the Global Clock Network (Part 1 of 2)
Dual-
Purpose
Clock Pin
GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7
DPCLK0 (1)
———
v
————
DPCLK1 (1)
——
v
—————
DPCLK2
v
———————
DPCLK3
————
v
———
DPCLK4
——————
v
—
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