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器件3D模型￥ 72.455
EP1C4F400C8N 数据手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
FBGA-400
描述:
可编程逻辑器件(CPLD/FPGA) EP1C4F400C8N FBGA-400
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P162P314P317P377Hot
典型应用电路图在P25P27P29P31P255P273
原理图在P22P141P341
封装尺寸在P12P117P377P383P384
型号编码规则在P11P117
功能描述在P21P148P149P150P152P336P338P340
技术参数、封装参数在P85P86P87P88P89P90P94P113P114P142P224P225
应用领域在P102P203P228
电气规格在P225
导航目录
EP1C4F400C8N数据手册
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Altera Corporation 11–7
May 2008 Preliminary
Power-Up Sequence
1 The maximum DC current when hot-socketing Cyclone devices
is less than 300 µA, whereas the maximum AC current during
hot-socketing is less than 8 mA for a period of 10ns or less.
During hot-socketing, the signal pins of a device may be connected and
driven by the active system before the power supply can provide current
to the device V
CC
and ground planes. Known as latch-up, this condition
can cause parasitic diodes to turn on within the device, causing the device
to consume a large amount of current, and possibly causing electrical
damage. This operation can also cause parasitic diodes to turn on inside
of the driven device. Cyclone devices are immune to latch-up when hot-
socketing.
Power-Up
Sequence
Because Cyclone devices can be used in a multi-voltage environment,
they are designed to tolerate any possible power-up sequence. Either
V
CCINT
or V
CCIO
can initially supply power to the device, and 3.3-V, 2.5-V,
1.8-V, or 1.5-V input signals can drive the devices without special
precautions before V
CCINT
or V
CCIO
is applied. Cyclone devices can
operate with a V
CCIO
voltage level that is higher than the V
CCINT
level. You
can also change the V
CCIO
supply voltage while the board is powered-up.
However, you must ensure that the V
CCINT
and V
CCIO
power supplies stay
within the correct device operating conditions.
When V
CCIO
and V
CCINT
are supplied from different power sources to a
Cyclone device, a delay between V
CCIO
and V
CCINT
may occur. Normal
operation does not occur until both power supplies are in their
recommended operating range. When V
CCINT
is powered-up, the IEEE
Std. 1149.1 Joint Test Action Group (JTAG) circuitry is active. If TMS and
TCK are connected to V
CCIO
and V
CCIO
is not powered-up, the JTAG
signals are left floating. Thus, any transition on TCK can cause the state
machine to transition to an unknown JTAG state, leading to incorrect
operation when V
CCIO
is finally powered-up. To disable the JTAG state
during the power-up sequence, TCK should be pulled low to ensure that
an inadvertent rising edge does not occur on TCK.
Power-On Reset
When designing a circuit, it is important to consider system state at
power-up. Cyclone devices maintain a reset state during power-up.
When power is applied to a Cyclone device, a power-on-reset event
occurs if V
CC
reaches the recommended operating range within a certain
period of time (specified as a maximum V
CC
rise time). A POR event does
not occur if these conditions are not met because slower rise times can
cause incorrect device initialization and functional failure. The V
CCIO
level of the I/O banks that contains configuration pins must also reach an
acceptable level to trigger POR event.
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