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EP4CE6E22I8LN 数据手册 - Intel（英特尔）
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EP4CE6E22I8LN数据手册
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Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices 2–5
Logic Array Blocks
November 2009 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Logic Array Blocks
Logic array blocks (LABs) contain groups of LEs.
Topology
Each LAB consists of the following features:
■ 16 LEs
■ LAB control signals
■ LE carry chains
■ Register chains
■ Local interconnect
The local interconnect transfers signals between LEs in the same LAB. Register chain
connections transfer the output of one LE register to the adjacent LE register in an
LAB. The Quartus II Compiler places associated logic in an LAB or adjacent LABs,
allowing the use of local and register chain connections for performance and area
efficiency.
Figure 2–4 shows the LAB structure for Cyclone IV devices.
Figure 2–4. Cyclone IV Device LAB Structure
Direct link
interconnect
from adjacent
block
Direct link
interconnect
to adjacent
block
Row Interconnect
Column
Interconnect
Local Interconnect
LAB
Direct link
interconnect
from adjacent
block
Direct link
interconnect
to adjacent
block
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