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EPM3064ALC44-10N 数据手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
CPLD芯片
封装:
PLCC-44
描述:
ALTERA EPM3064ALC44-10N 芯片, CPLD, MAX 3000A, 64宏单元, PLCC44
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EPM3064ALC44-10N数据手册
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2 Altera Corporation
Preliminary
MAX 7000AE, MAX 7000B, & MAX 3000A Devices
I/O Transients
During Fast
V
ccint
Rise
Altera has identified that fast V
CCINT
rise times can lead to pulses on I/O
pins during the power-up period on MAX
®
7000AE, MAX 3000A, and
MAX 7000B devices. This condition can violate the hot-socketing
definition that says these pins should be tri-stated during power-up and
should not source or sink more than 300 μA of current per pin. There are
two different pulses resulting from fast V
CCINT
rise times, a low pulse
transient on any I/O pin, and a separate pulse transient on combinatorial
output pins.
Table 3 shows the issues and the MAX devices they affect.
Table 2. MAX 7000B I/O Current During Power Sequencing Issues
Power Sequence Situation Issue Workarounds (2)
V
CCIO
is ramped before V
CCINT
and V
CCIO
rise time is slower than 10 ms.
All I/O pins will drive high (source
current of up to 45 mA) until V
CCINT
ramps. (1)
1. Ramp V
CCINT
before
V
CCIO
ramps
or
2. Decrease V
CCIO
rise time
to faster than 10 ms
V
CCINT
and V
CCIO
are grounded and a
particular I/O pin voltage rises from
0 to 3.3V slower than 10 ms.
That particular I/O pin will sink up to
24 mA, pulling the I/O pin voltage
down, until V
CCINT
or V
CCIO
ramps.
1. Ramp V
CCINT
or V
CCIO
before I/O pin voltage
ramps
or
2. Decrease I/O pin voltage
rise time to faster than 10
ms.
Notes to Ta b l e 2:
(1) The device's I/O source current does not pose any reliability issues unless it is maintained for an extended period
of time.
(2) If the source/sink current is not a concern in the system during power-up, no action is necessary.
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