Datasheet 搜索 > PLC可编程逻辑控制器 > Lattice Semiconductor（莱迪思） > ISPGAL22V10AB-75LN 数据手册 > ISPGAL22V10AB-75LN 数据手册 5/20 页
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ISPGAL22V10AB-75LN 数据手册 - Lattice Semiconductor（莱迪思）
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Lattice Semiconductor（莱迪思）
分类:
PLC可编程逻辑控制器
封装:
QFN-32
描述:
SPLD - 简单可编程逻辑器件 PROGRAMMABLE LO VOLT E2CMOS PLD
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ISPGAL22V10AB-75LN数据手册
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Lattice Semiconductor ispGAL22V10AV/B/C Data Sheet
3
NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin
defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins.
Combinatorial I/O
In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate.
Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true
(active high) or inverted (active low). Output tri-state control is available as an individual product-term for each out-
put, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “prod-
uct-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both
polarities (true and inverted) of the pin are fed back into the AND array.
Figure 3. Registered Mode
Figure 4. Combinatorial Mode
ACTIVE HIGHACTIVE LOW
S
0
= 0
S
1
= 0
S
0
= 1
S
1
= 0
AR
SP
D
Q
Q
CLK
AR
SP
D
Q
QCLK
ACTIVE HIGHACTIVE LOW
S
0
= 1
S
1
= 1
S
0
= 0
S
1
= 1
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