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Figure 15-1. Ethernet Controller
ARM Cortex M3
Ethernet Controller
Media
Access
Controller
Physical
Layer Entity
MAC
(Layer 2)
PHY
(Layer 1)
RJ45
Magnetics
Figure 15-2 on page 551 shows more detail of the internal structure of the Ethernet Controller and
how the register set relates to various functions.
Figure 15-2. Ethernet Controller Block Diagram
MACRIS
MACIACK
MACIM
Interrupt
Control
MACRCTL
MACNP
Receive
Control
MACTCTL
MACTHR
MACTR
Transmit
Control
Transmit
FIFO
Receive
FIFO
MACIA0
MACIA1
Individual
Address
MACMCTL
MACMDV
MII
Control
MACDDATA
Data
Access
TXOP
TXON
RXIP
RXIN
MDIX
Clock
Reference
Transmit
Encoding
Pulse
Shaping
Receive
Decoding
Clock
Recovery
Auto
Negotiation
Carrier
Sense
MR3
MR0
MR1
MR2
MR4
Media Independent Interface
Management Register Set
MR5
MR18
MR6
MR16
MR17
MR19
MR23
MR24
Collision
Detect
XTALNPHY
XTALPPHY
LED0
LED1
MACMTXD
MACMRXD
Interrupt
15.2 Signal Description
Table 15-1 on page 552 and Table 15-2 on page 552 list the external signals of the Ethernet Controller
and describe the function of each. The Ethernet LED signals are alternate functions for GPIO signals
and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists
the GPIO pin placement for the LED signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 309) should be set to choose the LED function. For more information
on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 287. The remaining
signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin assignment
and function.
551July 15, 2014
Texas Instruments-Production Data
Stellaris
®
LM3S6965 Microcontroller

LM3S6965-IQC50-A2T 数据手册

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LM3S6965IQC50A2 数据手册

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TEXAS INSTRUMENTS  LM3S6965-IQC50-A2  微控制器, 32位, ARM 皮质-M3, 50 MHz, 256 KB, 64 KB, 100 引脚, LQFP
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的Stellaris LM3S6965微控制器 Stellaris LM3S6965 Microcontroller
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