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LT1160IS#TRPBF 数据手册 - Linear Technology（凌力尔特）
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Linear Technology（凌力尔特）
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负载控制器
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SOIC-14
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LT1160IS#TRPBF数据手册
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3
LT1160/LT1162
11602fb
I
UVOUT
Undervoltage Output Leakage V
+
= 15V ● 0.1 5 µA
V
UVOUT
Undervoltage Output Saturation V
+
= 7.5V, I
UVOUT
= 2.5mA ● 0.2 0.4 V
V
OH
Top Gate ON Voltage V
INTOP
= 2V, V
INBOTTOM
= 0.8V ● 11 11.3 12 V
Bottom Gate ON Voltage V
INTOP
= 0.8V, V
INBOTTOM
= 2V ● 11 11.3 12 V
V
OL
Top Gate OFF Voltage V
INTOP
= 0.8V, V
INBOTTOM
= 2V ● 0.4 0.7 V
Bottom Gate OFF Voltage V
INTOP
= 2V, V
INBOTTOM
= 0.8V ● 0.4 0.7 V
t
r
Top Gate Rise Time V
INTOP
(+) Transition, V
INBOTTOM
= 0.8V, ● 130 200 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Rise Time V
INBOTTOM
(+) Transition, V
INTOP
= 0.8V, ● 90 200 ns
Measured at V
BGATE DR
(Note 5)
t
f
Top Gate Fall Time V
INTOP
(–) Transition, V
INBOTTOM
= 0.8V, ● 60 140 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Fall Time V
INBOTTOM
(–) Transition, V
INTOP
= 0.8V, ● 60 140 ns
Measured at V
BGATE DR
(Note 5)
t
D1
Top Gate Turn-On Delay V
INTOP
(+) Transition, V
INBOTTOM
= 0.8V, ● 250 500 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Turn-On Delay V
INBOTTOM
(+) Transition, V
INTOP
= 0.8V, ● 200 400 ns
Measured at V
BGATE DR
(Note 5)
t
D2
Top Gate Turn-Off Delay V
INTOP
(–) Transition, V
INBOTTOM
= 0.8V, ● 300 600 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Turn-Off Delay V
INBOTTOM
(–) Transition, V
INTOP
= 0.8V, ● 200 400 ns
Measured at V
BGATE DR
(Note 5)
t
D3
Top Gate Lockout Delay V
INBOTTOM
(+) Transition, V
INTOP
= 2V, ● 300 600 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Lockout Delay V
INTOP
(+) Transition, V
INBOTTOM
= 2V, ● 250 500 ns
Measured at V
BGATE DR
(Note 5)
t
D4
Top Gate Release Delay V
INBOTTOM
(–) Transition, V
INTOP
= 2V, ● 250 500 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Release Delay V
INTOP
(–) Transition, V
INBOTTOM
= 2V, ● 200 400 ns
Measured at V
BGATE DR
(Note 5)
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C.Test Circuit, T
A
= 25°C, V
+
= V
BOOST
= 12V, V
TSOURCE
= 0V, C
GATE
=
3000pF. Gate Feedback pins connected to Gate Drive pins, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: For the LT1160, Pins 1, 10 should be connected together. For the
LT1162, Pins 1, 7, 14, 20 should be connected together.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formulas:
LT1160CN/LT1160IN: T
J
= T
A
+ (P
D
)(70°C/W)
LT1160CS/LT1160IS: T
J
= T
A
+ (P
D
)(110°C/W)
LT1162CN/LT1162IN: T
J
= T
A
+ (P
D
)(58°C/W)
LT1162CS/LT1162IS: T
J
= T
A
+ (P
D
)(80°C/W)
Note 4: I
S
is the sum of currents through SV
+
, PV
+
and Boost pins.
I
BOOST
is the current through the Boost pin. Dynamic supply current is
higher due to the gate charge being delivered at the switching frequency.
See Typical Performance Characteristics and Applications Information
sections. The LT1160 = 1/2 LT1162.
Note 5: See Timing Diagram. Gate rise times are measured from 2V to 10V
and fall times are measured from 10V to 2V. Delay times are measured
from the input transition to when the gate voltage has risen to 2V or
decreased to 10V.
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