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M25P40-VMN3
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  • 典型应用电路图在P2
  • 原理图在P3
  • 型号编码规则在P5
  • 封装信息在P5
  • 技术参数、封装参数在P7
  • 型号编号列表在P1
M25P40-VMN3数据手册
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M25PXX
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Table 3. Instruction Set
Table 4. Status Register Format
Instruction Description One-byte Instruction Code
Address
Bytes
Dummy
Bytes
Data
Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to
WRSR Write Status Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RES
Release from Deep Power-down,
and Read Electronic Signature
1010 1011 ABh
0 3 1 to
Release from Deep Power-down 0 0 0
b7 b0
SRWD 0 0 BP2 BP1 BP0 WEL WIP
Status Register
Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit

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