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MCP3901A0T-E/ML 数据手册 - Microchip（微芯）
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MCP3901A0T-E/ML数据手册
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© 2011 Microchip Technology Inc. DS22192D-page 5
MCP3901
AC Power Supply Rejection AC PSRR — -77 — dB AV
DD
and DV
DD
= 5V +
1V
PP
@ 50/60 Hz
DC Power Supply Rejection DC PSRR — -77 — dB AV
DD
and DV
DD
= 4.5 to
5.5V
DC Common-Mode Rejection
Ratio (Note 2)
CMRR — -72 — dB V
CM
varies from -1V to
+1V
Oscillator Input
Master Clock Frequency Range MCLK 1 — 16.384 MHz (Note 8)
Power Specifications
Operating Voltage, Analog AV
DD
4.5 — 5.5 V
Operating Voltage, Digital DV
DD
2.7 3.6 5.5 V
Power On Reset Threshold POR — 4.2 — V (Note 3)
— 4.6 — -40°C < T
A
< 125°C,
(Note 3)
Operating Current, Analog
(Note 4)
AI
DD
— 2.1 2.8 mA BOOST<1:0> = 00
— 2.1 3.3 mA -40°C < T
A
< 125°C,
BOOST<1:0> = 00
— 3.8 5.6 mA BOOST<1:0> = 11
— 3.8 7 mA -40°C < T
A
< 125°C,
BOOST<1:0> = 11
Operating Current, Digital DI
DD
—0.451.0mADV
DD
= 5V,
MCLK = 4 MHz
— 0.25 0.45 mA DV
DD
= 2.7V,
MCLK = 4 MHz
—1.21.6mADV
DD
= 5V,
MCLK = 8.192 MHz
Shutdown Current, Analog I
DDS,A
—— 1µAAV
DD
pin only (Note 5)
Shutdown Current, Digital I
DDS,D
—— 1µADV
DD
pin only (Note 5)
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, AV
DD
= 4.5 to 5.5V, DV
DD
= 2.7 to 5.5V; -40°C < T
A
< +85°C,
MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V
IN
= -0.5 dBFS = 333 mV
RMS
@ 50/60 Hz
Parameters Symbol Min Typical Max Units Conditions
Note 1: This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance is specified at -0.5 dB below the
maximum signal range, V
IN
= -0.5 dBFS @ 50/60 Hz = 353 mV
RMS,
V
REF
= 2.4V.
2: See terminology section for definition.
3: This parameter is established by characterization and not 100% tested.
4: For these operating currents, the following bit settings apply: SHUTDOWN<1:0> = 00, RESET<1:0> = 00,
VREFEXT = 0, CLKEXT = 0.
5: For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> = 11,
VREFEXT = 1, CLKEXT = 1.
6: Applies to all gains. Offset error is dependant on PGA gain setting (see Figure 2-19 for typical values).
7: Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied
continuously to the part with no risk for damage.
8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with
BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz,
AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to ‘0’.
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