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器件3D模型￥ 6.131
PIC16F1823T-E/ST 数据手册 - Microchip（微芯）
制造商:
Microchip（微芯）
封装:
TSSOP
描述:
8月14日引脚闪存单片机采用nanoWatt XLP技术 8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P13P14P15P16P17P127P200P202P209P316Hot
典型应用电路图在P317
原理图在P12P20P55P66P75P99P127P131P133P149P154P160
封装尺寸在P373
标记信息在P371P372
封装信息在P371P382
功能描述在P307
技术参数、封装参数在P57P61P87P104P131P134P144P147P163P164P170P259
应用领域在P53P57P58P211P217
电气规格在P57P61P87P131P134P144P147P163P164P170P310
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PIC16F1823T-E/ST数据手册
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PIC12F/LF1822/16F/LF1823
DS41413A-page 202 Preliminary 2010 Microchip Technology Inc.
23.2 Compare Mode
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPR1H:CCPR1L
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
• Toggle the CCP1 output
• Set the CCP1 output
• Clear the CCP1 output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCP1M<3:0> control bits of the CCP1CON register. At
the same time, the interrupt flag CCP1IF bit is set.
All Compare modes can generate an interrupt.
Figure 23-2 shows a simplified diagram of the
Compare operation.
FIGURE 23-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
23.2.1 CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the associated TRIS bit.
Also, the CCP1 pin function may be moved to
alternative pins using the APFCON register. Refer to
Section 12.1 “Alternate Pin Function” for more
details.
23.2.2 TIMER1 MODE RESOURCE
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
See Section 20.0 “Timer1 Module with Gate Control”
for more information on configuring Timer1.
23.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 module does not
assert control of the CCP1 pin (see the CCP1CON
register).
23.2.4 SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCP1M<3:0> = 1011), the CCP1 module does the
following:
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
The CCP1 module does not assert control of the CCP1
pin in this mode.
The Special Event Trigger output of the CCP1 occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPR1H, CCPR1L
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. The
Special Event Trigger output starts an A/D conversion
(if the A/D module is enabled). This allows the
CCPR1H, CCPR1L register pair to effectively provide a
16-bit programmable period register for Timer1.
23.2.5 COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (F
OSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
Note: Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the PORT I/O
data latch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
R
Output
Logic
Special Event Trigger
Set CCP1IF Interrupt Flag
(PIR1)
Match
TRIS
CCP1M<3:0>
Mode Select
Output Enable
Pin
Special Event Trigger will:
• CCP1: Reset Timer1, but not set interrupt flag bit TMR1IF
and set bit GO/DONE
(ADCON0<1>).
CCP1
4
Note: Clocking Timer1 from the system clock
(F
OSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCP1
pin, TImer1 must be clocked from the
instruction clock (F
OSC/4) or from an
external clock source.
Note 1: The Special Event Trigger from the CCP1
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will preclude
the Reset from occurring.
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