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PIC18F4685-E/ML
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PIC18F4685-E/ML数据手册
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PIC18F2682/2685/4682/4685
DS39761B-page 10 Preliminary © 2007 Microchip Technology Inc.
FIGURE 1-1: PIC18F2682/2685 (28-PIN) BLOCK DIAGRAM
Instruction
Decode &
Control
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/SS
/HLVDIN
RB0/INT0/AN10
RC0/T1OSO/T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
RB1/INT1/AN8
Data Latch
Data Memory
(3.3 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
44
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
8
8
ALU<8>
Address Latch
Program Memory
(80/96 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
RB2/INT2/CANTX
RB3/CANRX
PCLATU
PCU
PORTE
MCLR/VPP/RE3
(1)
OSC2/CLKO/RA6
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
RB4/KBI0/AN9
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
EUSART
MSSP
10-bit
ADC
Timer2Timer1 Timer3Timer0
ECCP1
HLVD
CCP1
BOR
Data
EEPROM
W
Instruction Bus <16>
STKPTR
Bank
8
State Machine
Control Signals
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1
(2)
OSC2
(2)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Reference
Band Gap
V
SS
MCLR
(1)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
OSC1/CLKI/RA7
ECAN™
BITOP
FSR0
FSR1
FSR2
inc/dec
Address
12
Decode
logic

PIC18F4685-E/ML 数据手册

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