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器件3D模型￥ 34.818
PIC18F4685-E/ML 数据手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
QFN-44
描述:
PIC18 系列 3328 B RAM 96 kB 闪存 8位 微控制器 - QFN-44
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P4P5P167P169P176Hot
典型应用电路图在P193
原理图在P10P12P13P27P43P146P150P154P160P162P168P169
封装尺寸在P459
标记信息在P457P458
封装信息在P457P459P460P461P462P463
技术参数、封装参数在P432P433P434P436P437P438
应用领域在P180P272
电气规格在P107P260P261P265P266
导航目录
PIC18F4685-E/ML数据手册
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PIC18F2682/2685/4682/4685
DS39761B-page 152 Preliminary © 2007 Microchip Technology Inc.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
•Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (Fosc/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and RC0/
T1OSO/T13CKI pins become inputs. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 12-1: TIMER1 BLOCK DIAGRAM
FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Sleep Input
T1OSCEN
(1)
FOSC/4
Internal
Clock
On/Off
1
0
2
T1OSO/T13CKI
T1OSI
1
0
TMR1ON
TMR1L
Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP1 Special Event Trigger)
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer1
Prescaler
1, 2, 4, 8
Synchronize
Detect
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Sleep Input
T1OSCEN
(1)
FOSC/4
Internal
Clock
1
0
2
T1OSO/T13CKI
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR1L
Internal Data Bus
8
Set
TMR1IF
on Overflow
TMR1
TMR1H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR1ON
Clear TMR1
(CCP1 Special Event Trigger)
Timer1 Oscillator
On/Off
Timer1
Prescaler
1, 2, 4, 8
Synchronize
Detect
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