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PIC18F4685-E/ML
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PIC18F4685-E/ML数据手册
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PIC18F2682/2685/4682/4685
DS39761B-page 160 Preliminary © 2007 Microchip Technology Inc.
14.1 Timer3 Operation
Timer3 can operate in one of three modes:
•Timer
Synchronous Counter
Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (F
OSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator if enabled.
As with Timer1, the RC1/T1OSI and RC0/T1OSO/
T13CKI pins become inputs when the Timer1 oscillator
is enabled. This means the values of TRISC<1:0> are
ignored and the pins are read as ‘0’.
FIGURE 14-1: TIMER3 BLOCK DIAGRAM
FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Sleep Input
T1OSCEN
(1)
FOSC/4
Internal
Clock
1
0
2
T1OSO/T13CKI
T1OSI
1
0
TMR3ON
TMR3L
Set
TMR3IF
on Overflow
TMR3
High Byte
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer3
CCP1/ECCP1 Special Event Trigger
TCCPx
Clear TMR3
Prescaler
1, 2, 4, 8
Synchronize
Detect
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Sleep Input
T1OSCEN
(1)
FOSC/4
Internal
Clock
1
0
2
T1OSO/T13CKI
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR3L
Internal Data Bus
8
Set
TMR3IF
on Overflow
TMR3
TMR3H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR3ON
CCP1/ECCP1 Special Event Trigger
Timer1 Oscillator
On/Off
Timer3
Timer1 clock input
TCCPx
Clear TMR3
Prescaler
1, 2, 4, 8
Synchronize
Detect

PIC18F4685-E/ML 数据手册

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484 页 / 7.96 MByte
Microchip(微芯)
56 页 / 0.37 MByte
Microchip(微芯)
8 页 / 0.22 MByte
Microchip(微芯)
2 页 / 0.11 MByte

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