器件3D模型

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R5F52105BDFN#V0 数据手册 - Renesas Electronics（瑞萨电子）

制造商:

Renesas Electronics（瑞萨电子）

分类:

微控制器

封装:

LQFP

描述:

RX210 微控制器RX210 低功率微控制器具有宽工作范围并且可以在高达 50 MHz 78 DMIPS 时执行计算。使用 RX210 的应用包括数码相机、洗衣机、功率计、智能手机、医疗保健设备和冰箱。工作范围：1.62 V 至 5.3 V 事件链接控制器 (ELC) 多功能引脚控制器 (MPC) 三相电动机控制计时器 (MTU2) 12 位模/数转换器 4 种功耗模式： -睡眠模式 -所有模块时钟停止模式 -软件待机模式 -深度软件待机模式 ### RX 系列微控制器，Renesas ElectronicsRX 系列 32 位闪存微控制器持续发展，用于工业、消费品和办公自动化应用。

Pictures:

3D模型

符号图

焊盘图

引脚图

产品图

页面导航:

引脚图在P13P14P15P16P17P18P19P20P21P22P23P24Hot

原理图在P12

封装尺寸在P17P153P154P155P156P157P158P159P160P161

功能描述在P2P3P4P5

技术参数、封装参数在P2P3P4P5P64

电气规格在P64P65P66P67P68P69P70P71P72P73P74P75

导航目录

引脚图在P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24
原理图在P12
封装尺寸在P17 P153 P154 P155 P156 P157 P158 P159 P160 P161
功能描述在P2 P3 P4 P5
技术参数、封装参数在P2 P3 P4 P5 P64
电气规格在P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75

R5F52105BDFN#V0数据手册

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R01DS0041EJ0120 Rev.1.20 Page 4 of 162

Nov 28, 2012

RX210 Group 1. Overview

Timers Multi-function timer pulse

unit 2 (MTU2a)

 (16 bits  6 channels)  1 unit

 Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and

three pulse-input lines

 Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,

PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than

channel 5, for which only four signals are available.

 Input capture function

 21 output compare/input capture registers

 Pulse output mode

 Complementary PWM output mode

 Reset synchronous PWM mode

 Phase-counting mode

 Generation of triggers for A/D converter conversion

Port output enable 2

(POE2a)

Controls the high-impedance state of the MTU’s waveform output pins

8-bit timer (TMR)

 (8 bits  2 channels)  2 units

 Select from among seven internal clock signals (PCLK1, PCLK/2, PCLK/8, PCLK/32, PCLK/64,

PCLK/1024, PCLK/8192) and one external clock signal

 Capable of output of pulse trains with desired duty cycles or of PWM signals

 The 2 channels of each unit can be cascaded to create a 16-bit timer

 Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12

Compare match timer

(CMT)

 (16 bits  2 channels)  2 units

 Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)

Watchdog timer (WDTA)

 14 bits  1 channel

 Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512,

PCLK/2048, PCLK/8192)

Independent watchdog

timer (IWDTa)

 14 bits  1 channel

 Counter-input clock: IWDT-dedicated on-chip oscillator

Frequency divided by 1, 16, 32, 64, 128, or 256

Realtime clock (RTCb)

 Clock source: Sub-clock

 Time/calendar

 Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt

 Time-capture facility for three values

Communication

function

Serial communications

interfaces (SCIc, SCId)

 7 channels (channel 0, 1, 5, 6, 8, 9: SCIc, channel 12: SCId)

 Serial communications modes:

Asynchronous, clock synchronous, and smart-card interface

 On-chip baud rate generator allows selection of the desired bit rate

 Choice of

LSB-first or MSB-f

irst transfer

 Average transfer rate clock can be input from TMR timers (SCI5, SCI6, and SCI12)

 Simple IIC

 Simple SPI

 Master/slave mode supported (SCId only)

 Start frame and information frame are included (SCId only)

C bus interface (RIIC)

 1 channel

 Communications formats:

C bus format/SMBus format

 Master/slave selectable

 Supports the fast mode

Serial peripheral

interface (RSPI)

 1 channel

 Transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI

clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-

synchronous operation (three lines)

 Capable of handling serial transfer as a master or slave

 Data formats

 Choice of LSB-first or MSB-first transfer

The number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32

bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with each frame

having up to 32 bits)

 Double buffers for both transmission and reception

Table 1.1 Outline of Specifications (3 / 4)

Classification Module/Function Description

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